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LT5546EUF#PBF

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Texas Instruments Incorporated - 8 -
GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP SLWS137A
This document contains information which may be changed at any time without notice
frequency and “Clock Rate” is the chip’s clock rate. The frequency register is double buffered so that
frequency changes can be made synchronous to external sync signals.
The upper 16 bits of the current phase increment is monitored by the phase increment register. The
register tracks the current phase increment when the “hold” control is low and holds the last value when
“hold” is high. The user may wish to monitor the phase increment in order to reinitialize the PLL after a loss
of signal, or to determine when carrier lock has been achieved.
2.9 NCO
The PLL circuit generates a phase increment word which is used by the NCO to generate a
sine/cosine sequence at the desired tuning frequency. The NCO circuit accumulates the phase and uses
the upper 13 bits of the 32 bit accumulator to lookup 12 bit sines and cosines. A block diagram of the NCO
circuit is shown in Figure 6.
Figure 6. NCO CIRCUIT
The accumulator output plus one half the phase increment is used in the high speed mode
1
to look
up the BCOS and BSIN values. This generates the proper “odd time” sine/cosine values needed in the high
speed mode. The tuning range in the high speed mode is limited to +/- F
IN
/4, where F
IN
is thehigh speed
input data rate. To tune to frequencies above F
IN
/4, the user must negate the odd-time output samples (both
I and Q). This mixes the output down by F
IN
/2. For example, to mix down the frequency 0.3
IN
, the user
should set the tuning frequency to +0.2F
IN
, and then negate the odd-time output data to give a final tuning
of (0.2F
IN
- 0.5F
IN
) = -0.3F
IN
.
The dither circuit adds a random value to the upper 17 bits of the accumulator output. The random
number sequence is initialized to zero by the dither sync input. The dithering can be turned off by forcing
the sync to be active. The BSIN output is negated if the high speed mode is not enabled.
2.10 SNAPSHOT RAM
The snapshot RAM is used to store blocks of 64 mixer and NCO outputs. The mixer outputs are the
SI and SQ outputs shown in Figure 3. The NCO samples are the ACOS and ASIN values shown in Figure
3. The NCO samples are delayed to match the pipeline delay from the XI and XQ inputs to the SI and SQ
1. The high speed mode is the double rate real input mode, see Section 2.4
32 BIT PHASE ACCUMULATOR
NCO Sync
PHASE
INCREMENT
DIVIDE BY 2
Clear
Dither
Sync
High Speed
Mode
DITHER
TRIG
TABLE
ACOS
ASIN
13 Bits17 Bits
17 Bits
12 Bits
12 Bits
TRIG
TABLE
BCOS
BSIN
13 Bits
12 Bits
12 Bits
Negate Sine
CIN
Texas Instruments Incorporated - 9 -
GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP SLWS137A
This document contains information which may be changed at any time without notice
outputs. The snapshot can be programmed to store every sample, every other sample, every third sample,
or every fourth sample. The rate control is primarily used when capturing samples of offset-QPSK data
which is processed by the chip at twice the baud rate. Only every other sample of the offset-QPSK sample
is of interest.
The snapshot can be triggered by the input syncs, the delayed input syncs, the sync counter’s
terminal count or the snap sync input. Once triggered, the snapshot start time can be delayed by up to 256
sample clocks, where the sample clock rate is dependant upon the snapshot rate control.
The snapshot RAM is a read only memory which is read using addresses 256 through 511 of the
control interface. Addresses 256 through 319 read SI, addresses 320 through 383 read SQ, addresses 384
through 447 read ASIN, and addresses 448 through 511 read ACOS. The 12 bit values are sign extended
to 16 bits in the control interface.
2.11 OUTPUT FORMAT
The chip has four 12 bit output ports labeled YA, YB, YC, and YD. Each port can be individually
configured to output mixer results (I
even
, Q
even
, I
odd
, Q
odd
), or symbol and NCO samples. The symbol and
NCO samples are the snapshot RAM inputs (SI, SQ, sine, cosine). The output selection is shown in Table
1 below:
The YA, YB, YC and YD outputs can be rounded to 12, 10 or 8 bits and can be masked to a desired
number of bits through the use of four 12 bit mask words. The masks are bitwise ANDed with the output
words to selectively clear the output bits.
Output enable controls are provided to individually turn off these outputs.
2.12 DATA DELAYS
The data delay through the chip in input clock cycles is shown in Table 2 below.
Table 1: OUTPUT SELECTION
OUTPUT
PORT
OUTPUT SELECT
01
YA I
even
SI
YB Q
even
SQ
YC I
odd
cosine
YD Q
odd
sine
Table 2: DATA DELAYS
FROM TO DELAY MODE
I, Q SI, SQ 15 OUTSEL=1
I, Q I, Q (even/odd) 13 OUTSEL=0
Texas Instruments Incorporated - 10 -
GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP SLWS137A
This document contains information which may be changed at any time without notice
2.13 POWER DOWN MODES
The chip has a power down and clock loss detect circuit. This circuit detects if the clock is absent
long enough to cause dynamic storage nodes to lose state. If clock loss is detected, an internal reset state
is entered to force the dynamic nodes to become static. The control registers are not reset and will retain
their values, but any data values within the chip will be lost. When the clock returns to normal the chip will
automatically return to normal. In the reset state the chip consumes only a small amount of standby power.
The user can select whether this circuit is in the automatic clock-loss detect mode, is always on (power down
mode), or is disabled (the clock reset never kicks in) using the POWER_DOWN control bits in address 1.
NOTE: The chip is in the power down mode when power is applied, and must be enabled by setting
the power down mode to "2" in register 1.
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LT5546EUF#PBF

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Manufacturer:
Analog Devices Inc.
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Modulator / Demodulator 17MHz Demodulator w. VGA
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