LT5546EUF#PBF Datasheet LT5546EUF#PBF, LT5546EUF#TRPBF | P4-P6

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GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP SLWS137A

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2.0 FUNCTIONAL DESCRIPTION

Fabricated in 0.5 micron CMOS technology, the GC3021A chip is designed to mix input data with

an internally generated sine/cosine sequence. The chip can be used as a signal mixer, or if the phase error

lookup and phase lock loop (PLL) circuitry is enabled, as a carrier removal circuit for signal demodulation.

The mixer accepts complex data at rates up to 100 MHz , or real samples at rates up to 200 MHz in the real

input mode . The chip mixes the input with a complex sinusoid, and outputs the results at a 100 MHz rate.

The input data in the real mode is assumed to be even/odd sample pairs. The 200 MHz input data

is split into even and odd samples streams, each at a rate of 100 million samples per second. The even and

odd time sample data streams are mixed with sines and cosines which have also been split into even and

odd time streams. The complex results are then output as two complex pairs at 100 MHz, one for the even

time samples and one for the odd time samples.

The frequency of the sine/cosine sequence is specified as a 32 bit phase word which drives a phase

accumulator. A carry input to the phase accumulator allows the user to extend the tuning resolution with an

external accumulator.

The GC3021A chip’s carrier removal mode allows the chip to be used as part of a QPSK/QAM

demodulator using decision error feed back to achieve carrier lock. A phase error feedback circuit uses the

upper 7 bits of the I and Q mixer outputs to lookup a one bit phase error term. The phase error lookup is

performed by mapping the I/Q pair into a single quadrant so that the lookup table address is only 12 bits (6

bits of I and 6 bits of Q). The 4096 bit lookup table is programmed by the user to output the sign of the phase

error for each possible I/Q pair. This phase error feeds a phase-lock-loop (PLL) circuit which adjusts the

sinusoid frequency to drive the average phase error to zero.

A snapshot RAM is included to store blocks of I/Q symbol outputs and the sine/cosine pairs used

to generate them. This information is used by an external DSP chip or microprocessor to lookup the symbol

error, to rotate the error by the sine/cosine phase, and then update equalizer coefficients.

On chip diagnostic circuits are provided to simplify system debug and maintenance.

The chip receives configuration and control information over a microprocessor compatible bus

consisting of a 16 bit data I/O port, a 9 bit address port, a read enable, a write enable, and a chip enable

strobe. The control registers, coefficient registers, phase error RAM and snapshot memory are mapped into

the 512 word address space of the control port.

A detailed description of the major circuits within the chip follows.

2.1 CONTROL INTERFACE

The control interface allows an external processor to configure the chip, to capture and read

samples from the chip and to perform diagnostics.

The chip is configured by writing control information into control registers within the chip. The

registers are written to or read from using the C[0:15], A[0:8], RE

, WE, and CE pins. Each control register

has been assigned a unique address within the chip. An external processor (a microprocessor, computer,

Texas Instruments Incorporated - 3 -

GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP SLWS137A

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or DSP chip) can write into a register by setting A[0:8] to the desired register address, setting the CE pin

low, setting C[0:15] to the desired value and then pulsing WE

low. RE must remain high.

To read from a control register the processor must set A[0:8] to the desired address, set CE

low,

and then set RE low. The chip will then drive C[0:15] with the contents of the selected register. After the

processor has read the value from C[0:15] it should set RE

and CE high. The C[0:15] pins are turned off

(high impedance) whenever CE

is high or WE is low. The chip will only drive these pins when both CE and

are low and WE is high.

If RE

is held low, then the interface will behave in the GC3021 mode, where CE is CS, and WE is

R/W

The chip’s control address space is divided into fourteen control registers, a test port, four DC offset

registers, 256 phase error memory words, and 256 snapshot memory words. The 14 control registers are

MODE_REG, SYNC_REG0, SYNC_REG1, DELAY_REG, COUNTER_REG, PLL_REG, FREQ_REG0,

FREQ_REG1, OUTPUT_REGA, OUTPUT_REGB, OUTPUT_REGC, OUTPUT_REGD, SNAP_REG, and

PHASE_REG. The control registers are mapped to addresses 0 to 13. See Section 4.0 for details about the

contents of these registers.

Address 14 is used to generate a one-shot pulse. This pulse, OS

, which is one clock cycle wide,

can be output from the chip on the SO pin or used to synchronize internal circuits. Address 15 is a read only

port used to monitor the power-down and keepalive clock functions for test. Addresses 16 through 19 are

the DC offset registers DC_I_IN, DC_Q_IN, DC_I_OUT, DC_Q_OUT.

Addresses 20 through 255 are unused.

Addresses 256 through 511 are shared between the phase error memory and the snapshot

memory. Reading from these addresses accesses the contents of the snapshot memory. Writing to these

addresses loads the phase error lookup memory.

2.2 SYNC COUNTER

The sync counter circuit is used to generate sync pulses for the chip. The circuit accepts two sync

inputs (SA and SB) and generates internal syncs and a sync out (SO) pulse. The circuit contains a 20 bit

counter which can be set to count in cycles of 16*(COUNT+1) clocks, where COUNT ranges from 0 to 2

-1.

The counter’s terminal count (TC) can be used as a synchronization pulse. The lower 12 bits from the

counter are used as input data during diagnostics.

The circuit can generate a one-shot pulse (OS) which can be used as a synchronization pulse.

The input syncs SA

and SB can be delayed by up to 258 clock cycles. The delayed syncs (DSA and

DSB) can be used to adjust the sync timing to meet system requirements.

The internal syncs are used to synchronize the counter, the symbol align circuit, the snapshot

memory, the phase lock loop circuit and NCO circuit. Each circuit can be independently synchronized to SA

SB, DSA, DSB, TC, OS, or left to free run. The sync output can also be chosen from these syncs.

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GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP SLWS137A

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2.3 CLOCK GENERATOR

The clock generator generates the internal clocks from the clock input (CK). Two clock enable

inputs (CKENA and CKENB) are used to enable or disable the clock. Both enables must be low for internal

clocks to be generated. The enables are clocked into the chip and are used to enable or disable the following

clock edge. The enables are designed to be used with the data valid strobes from the GC3021A digital

resampler and GC2011Adigital filter chips.

2.4 INPUT FORMAT

The input format circuit accepts complex data at the clock rate of the chip, or real data at twice the

clock rate of the chip. The input format circuit outputs pairs of samples to the mixer circuit where the pair is

either a complex data pair, or an even and odd time sample pair. A block diagram of the input circuit is

shown in Figure 2.

Figure 2. INPUT FORMAT CIRCUIT

The even/odd data inputs share pins with the I/Q complex data inputs. The I input pins are used as

the even time inputs and the Q pins are used as the odd time inputs. The even samples are assumed to

preceed the odd time samples. I.E., (X0, X2, X4, ...) are the even time samples, (X1, X3, X5,..) are the odd

time samples.

DATA

MUX

Diagnostic

Ramp

Data

Mixer

COMPLEX

DATA

Mode

Select

12 Bits

EVEN/ODD

PAIR

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P38

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Modulator / Demodulator 17MHz Demodulator w. VGA

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