Texas Instruments Incorporated - 21 -
GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP SLWS137A
This document contains information which may be changed at any time without notice
4.8 SNAPSHOT CONTROL REGISTER
Registers 12 controls the snapshot memory. The suggested default is 0002 (HEX).
ADDRESS 12: SNAP_REG
BIT
TYPE NAME DESCRIPTION
0,1 (LSB) R/W TRIGGER This control sets the trigger condition which will start a
snapshot once the ARMED bit is set. The trigger
conditions are to start:
TRIGGER DESCRIPTION
0 immediately,
1 when the SN
strobe is received,
2 when the SNAP_SYNC is received
(See Section 4.2),
3never
2 R/W ARMED The user sets this bit to arm the snapshot memory
so that it will start on the next trigger condition. The
chip clears this bit when the trigger occurs.
3 R/W DONE This bit goes high when the snapshot is complete.
4,5 R/W SNAP_RATE Determines the rate at which samples are stored
according to:
SNAP_RATE DESCRIPTION
0 every clock, full rate samples
1 every other clock, half rate samples
2every 3
rd
clock, third rate samples
3every 4
th
clock, quarter rate samples.
6,7 R/W - unused
8-15 (MSB) R/W SNAP_DELAY Delay from snapshot trigger until the start of snapshot.
The delay is:
SNAP_DELAY*(SNAP_RATE+1)
clock cycles where SNAP_DELAY ranges from 0 to 255.
4.9 PHASE REGISTER
Register 13 is a read only register used to monitor the upper 16 bits of the NCO’s phase increment.
See PHASE_HOLD in Section 4.5.
4.10 ONE SHOT ADDRESS
The one shot pulse is generated on the OS pin by writing to address 14. This is a write-only address.
The data written to it is irrelevant.
4.11 TEST OUTPUT REGISTER
Register address 15 is a read only port used to monitor the powerdown and clock loss modes. Bit
0 is low if the chip is in power down, and bit 1 is low if clock loss has been detected. Normally both bits will
read as 1.
