Texas Instruments Incorporated - 7 -
GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP SLWS137A
This document contains information which may be changed at any time without notice
The Qmap mode is used to map the I, Q complex pair into one quadrant for looking up the phase
error. This is possible when the signal’s constellation pattern has quadrant symmetry. If the pattern does
not exhibit symmetry, then the quadrant map mode should not be used.
The 6 bit I and Q values are used to lookup the phase error in a 4096 by 1 bit memory. In the Qmap
mode the phase error is inverted as necessary to map it back into the proper quadrant.
The memory is implemented using a 256 word by 16 bit RAM as shown in Figure 4. The RAM is
loaded as 256 sixteen bit words mapped to addresses 256 to 511 of the control interface. The RAM is a
write only memory.
The phase error is passed to the phase lock loop (PLL) circuit. The phase error is also output on
the EOUT pin of the chip for external use.
2.8 PHASE LOCK LOOP
The phase error drives the PLL circuit shown in Figure 5.
Figure 5. PLL CIRCUIT
The phase error can either come from an input pad or from the phase error RAM. The error is
multiplied by the two constants 2
-A
and 2
-B
. These multipliers treat a phase error of “0” as +1 and a phase
error of “1” as -1. The multipliers also have a clear mode so that 2
-A
or 2
-B
can be set to zero.
The tracking bandwidth and damping of the of the phase lock loop filter are set using the constants
A and B. The filter will be critically damped when A is approximately one-half of B. When critically damped
the tracking bandwidth and residual phase jitter of the loop are set by B. A small value for B results in a wide
bandwidth with lots of jitter, but fast acquisition. A large value of B narrows the bandwidth and reduces the
residual jitter, but increases the initial acquisition time. Values of B between 24 and 31 are suggested. Use
24 for initial acquisition and 31 for final tracking. The values of A and B are double buffered so that the loop
bandwidth can be changed synchronous to an external sync signal.
Initial acquisition can be greatly aided by presetting the PLL to an estimated frequency offset. This
is done by loading the frequency register with the estimated frequency.
In the mixer mode the PLL is turned off by clearing 2
-A
and 2
-B
, clearing the accumulator and setting
the frequency register to the desired tuning frequency. The 32 bit frequency word is set to the desired
frequency using the formula: , where “Frequency” is the desired
2
-A
or Clear
2
-B
or Clear
Error From
Phase RAM
External
FREQUENCY
32 BIT ERROR ACCUMULATOR
(32 BITS)
PLL Sync
Error Input
Phase
32 BITS
External
MUX
32 BITS
Increment
To NCO
To
Control
Interface
phase_hold
16 MSBs
LATCH
FREQ
Frequency
Clock Rate
-----------------------------
2
32
=
