IDT72V72100L10BB Datasheet IDT72V72100L10BB, IDT72V72100L10BBG, IDT72V72100L15BB | P16-P18

COMMERCIAL TEMPERATURE RANGE

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II

FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

SIGNAL DESCRIPTION

INPUTS:

DATA IN (D0 - Dn)

Data inputs for 72-bit wide data (D0 - D71), data inputs for 36-bit wide data

(D0 - D35) or data inputs for 18-bit wide data (D0 - D17).

CONTROLS:

MASTER RESET ( MRS )

A Master Reset is accomplished whenever the MRS input is taken to a LOW

state. This operation sets the internal read and write pointers to the first location

of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.

If FWFT/SI is LOW during Master Reset then the IDT Standard mode,

along with EF and FF are selected. EF will go LOW and FF will go HIGH. If

FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with

IR and OR, are selected. OR will go HIGH and IR will go LOW.

All control settings such as OW, IW, BM, BE, RM, PFM and IP are defined

during the Master Reset cycle.

During a Master Reset, the output register is initialized to all zeroes. A Master

Reset is required after power up, before a write operation can take place. MRS

is asynchronous.

See Figure 8, Master Reset Timing, for the relevant timing diagram.

PARTIAL RESET ( PRS )

A Partial Reset is accomplished whenever the PRS input is taken to a LOW

state. As in the case of the Master Reset, the internal read and write pointers

are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH,

and HF goes HIGH.

Whichever mode is active at the time of Partial Reset, IDT Standard mode

or First Word Fall Through, that mode will remain selected. If the IDT Standard

mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall

Through mode is active, then OR will go HIGH, and IR will go LOW.

Following Partial Reset, all values held in the offset registers remain

unchanged. The programming method (parallel or serial) currently active at

the time of Partial Reset is also retained. The output register is initialized to all

zeroes. PRS is asynchronous.

A Partial Reset is useful for resetting the device during the course of

operation, when reprogramming programmable flag offset settings may not be

convenient.

See Figure 9, Partial Reset Timing, for the relevant timing diagram.

RETRANSMIT ( RT )

The Retransmit operation allows data that has already been read to be

accessed again. There are 2 modes of Retransmit operation, normal latency

and zero latency. There are two stages to Retransmit: first, a setup procedure

that resets the read pointer to the first location of memory, then the actual

retransmit, which consists of reading out the memory contents, starting at the

beginning of the memory.

Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.

REN and WEN must be HIGH before bringing RT LOW. When zero latency is

utilized, REN does not need to be HIGH before bringing RT LOW.

If IDT Standard mode is selected, the FIFO will mark the beginning of the

Retransmit setup by setting EF LOW. The change in level will only be noticeable

if EF was HIGH before setup. During this period, the internal read pointer is

initialized to the first location of the RAM array.

When EF goes HIGH, Retransmit setup is complete and read operations

may begin starting with the first location in memory. Since IDT Standard mode

is selected, every word read including the first word following Retransmit setup

requires a LOW on REN to enable the rising edge of RCLK. See Figure 16,

Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.

If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit

setup by setting OR HIGH. During this period, the internal read pointer is set

to the first location of the RAM array.

When OR goes LOW, Retransmit setup is complete; at the same time, the

contents of the first location appear on the outputs. Since FWFT mode is selected,

the first word appears on the outputs, no LOW on REN is necessary. Reading

all subsequent words requires a LOW on REN to enable the rising edge of

RCLK. See Figure 17, Retransmit Timing (FWFT Mode), for the relevant timing

diagram.

In Retransmit operation, zero latency mode can be selected using the

Retransmit Mode (RM) pin during a Master Reset. This can be applied to both

IDT Standard mode and FWFT mode.

Note, the Read Chip Select (RCS) input must be LOW during Retransmit.

The RCS input enables/disables the REN input.

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

This is a dual purpose pin. During Master Reset, the state of the FWFT/

SI input determines whether the device will operate in IDT Standard mode or

First Word Fall Through (FWFT) mode.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode

will be selected. This mode uses the Empty Flag (EF) to indicate whether or

not there are any words present in the FIFO memory. It also uses the Full Flag

function (FF) to indicate whether or not the FIFO memory has any free space

for writing. In IDT Standard mode, every word read from the FIFO, including

the first, must be requested using the Read Enable (REN) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be

selected. This mode uses Output Ready (OR) to indicate whether or not there

is valid data at the data outputs (Q

n). It also uses Input Ready (IR) to indicate

whether or not the FIFO memory has any free space for writing. In the FWFT

mode, the first word written to an empty FIFO goes directly to Qn after three RCLK

rising edges, REN = LOW is not necessary. Subsequent words must be

accessed using the Read Enable (REN) and RCLK.

After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF

offsets into the programmable registers. The serial input function can only be

used when the serial loading method has been selected during Master Reset.

Serial programming using the FWFT/SI pin functions the same way in both IDT

Standard and FWFT modes.

WRITE CLOCK (WCLK)

A write cycle is initiated on the rising edge of the WCLK input. Data setup

and hold times must be met with respect to the LOW-to-HIGH transition of the

WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/

IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of

updating HF flag to LOW.) The Write and Read Clocks can either be

independent or coincident.

WRITE ENABLE ( WEN )

When the WEN input is LOW, data may be loaded into the FIFO RAM array

on the rising edge of every WCLK cycle if the device is not full. Data is stored

in the RAM array sequentially and independently of any ongoing read

operation.

When WEN is HIGH, no new data is written in the RAM array on each WCLK

cycle.

To prevent data overflow in the IDT Standard mode, FF will go LOW,

inhibiting further write operations. Upon the completion of a valid read cycle,

COMMERCIAL TEMPERATURE RANGE

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II

FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

FF will go HIGH allowing a write to occur. The FF is updated by two WCLK

cycles + tSKEW after the RCLK cycle.

To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting

further write operations. Upon the completion of a valid read cycle, IR will go

LOW allowing a write to occur. The IR flag is updated by two WCLK cycles +

tSKEW after the valid RCLK cycle.

WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.

READ CLOCK (RCLK)

A read cycle is initiated on the rising edge of the RCLK input. Data can be

read on the outputs, on the rising edge of the RCLK input. It is permissible to

stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and HF flags will

not be updated. (Note that RCLK is only capable of updating the HF flag to

HIGH.) The Write and Read Clocks can be independent or coincident.

READ ENABLE ( REN )

When Read Enable is LOW, data is loaded from the RAM array into the output

When the REN input is HIGH, the output register holds the previous data

and no new data is loaded into the output register. The data outputs Q0-Qn

maintain the previous data value.

In the IDT Standard mode, every word accessed at Qn, including the first

word written to an empty FIFO, must be requested using REN provided that RCS

is LOW. When the last word has been read from the FIFO, the Empty Flag (EF)

will go LOW, inhibiting further read operations. REN is ignored when the FIFO

is empty. Once a write is performed, EF will go HIGH allowing a read to occur.

The EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle.

In the FWFT mode, the first word written to an empty FIFO automatically goes

to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW

after the first write. REN and RCS do not need to be asserted LOW. In order

to access all other words, a read must be executed using REN and RCS must

be enabled LOW. The RCLK LOW-to-HIGH transition after the last word has

been read from the FIFO, Output Ready (OR) will go HIGH with a true read

(RCLK with REN = LOW; RCS = LOW), inhibiting further read operations. REN

is ignored when the FIFO is empty.

SERIAL CLOCK ( SCLK )

During serial loading of the programmable flag offset registers, a rising edge

on the SCLK input is used to load serial data present on the SI input provided

that the SEN input is LOW.

SERIAL ENABLE ( SEN )

The SEN input is an enable used only for serial programming of the offset

registers. The serial programming method must be selected during Master

Reset. SEN is always used in conjunction with LD. When these lines are both

LOW, data at the SI input can be loaded into the program register one bit for each

LOW-to-HIGH transition of SCLK.

When SEN is HIGH, the programmable registers retains the previous

settings and no offsets are loaded. SEN functions the same way in both IDT

Standard and FWFT modes.

OUTPUT ENABLE ( OE )

When Output Enable is enabled (LOW), the parallel output buffers receive

data from the output register. When OE is HIGH, the output data bus (Qn) goes

into a high impedance state. Note, during a Master or Partial Reset RCS can

be HIGH or LOW, OE is the only input that can place the output bus into High-

Impedance.

READ CHIP SELECT ( RCS )

The Read Chip Select input provides synchronous control of the Read

output port. When RCS goes LOW, the next rising edge of RCLK causes the

Qn outputs to go to the LOW Z state. When RCS goes HIGH, the next RCLK

rising edge causes the Qn outputs to return to HIGH Z. During a Master or Partial

Reset the RCS input can be HIGH or LOW. OE provides High-Impedance

control of the data outputs. If OE is LOW the data outputs will be Low-Impedance

regardless of RCS until the first rising edge of RCLK after reset is complete. Then

if RCS is HIGH the data outputs will go to High-Impedance.

During the time while RCS is HIGH (disabled) all read operations are

ignored. That is, the REN input is disabled and data is not clocked from the RAM

array to the output register.

The RCS input does not effect the operation of the flags. For example, when

the first word is written to an empty FIFO, the EF will still go from LOW to HIGH

based on a rising edge of RCLK, regardless of the state of the RCS input.

Also, when operating the FIFO in FWFT mode the first word written to an

empty FIFO will still be clocked through to the output register based on RCLK,

regardless of the state of RCS. The RCS pin must also be active (LOW) in order

to perform a Retransmit. See figure 12 for Read Cycle and Read Chip Select

Timing (IDT Standard Mode). See figure 15 for Read Cycle and Read Chip

Select Timing (First Word Fall Through Mode).

LOAD ( LD )

This is a dual purpose pin. During Master Reset, the state of the LD input,

along with FSEL0 and FSEL1, determines one of eight default offset values for

the PAE and PAF flags, along with the method by which these offset registers

can be programmed, parallel or serial (see Table 2). After Master Reset, LD

enables write operations to and read operations from the offset registers. Only

the offset loading method currently selected can be used to write to the registers.

Offset registers can be read only in parallel.

After Master Reset, the LD pin is used to activate the programming process

of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading

or parallel load or read of these offset values.

BUS-MATCHING (BM, IW, OW)

The pins BM, IW and OW are used to define the input and output bus widths.

During Master Reset, the state of these pins is used to configure the device bus

sizes. See Table 1 for control settings. All flags will operate on the word/byte

size boundary as defined by the selection of bus width. See Figure 4 for Bus-

Matching Byte Arrangement.

BIG-ENDIAN/LITTLE-ENDIAN ( BE )

During Master Reset, a LOW on BE will select Big-Endian operation. A

HIGH on BE during Master Reset will select Little-Endian format. This function

is useful when the following input to output bus widths are implemented: x72 to

x36, x72 to x18, x36 to x72 and x18 to x72. If Big-Endian mode is selected,

then the most significant byte (word) of the long word written into the FIFO will

be read out of the FIFO first, followed by the least significant long word. If Little-

Endian format is selected, then the least significant word of the long word written

into the FIFO will be read out first, followed by the most significant word. The

mode desired is configured during master reset by the state of the Big-Endian

(BE) pin. See Figure 4 for Bus-Matching Byte Arrangement.

PROGRAMMABLE FLAG MODE (PFM)

During Master Reset, a LOW on PFM will select Asynchronous Program-

mable flag timing mode. A HIGH on PFM will select Synchronous Programmable

COMMERCIAL TEMPERATURE RANGE

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II

FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM,

LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition

of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.

Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and

PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration is selected (PFM, HIGH during

MRS) , the PAE is asserted and updated on the rising edge of RCLK only and

not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK

only and not RCLK. The mode desired is configured during master reset by

the state of the Programmable Flag Mode (PFM) pin.

INTERSPERSED PARITY (IP)

During Master Reset, a LOW on IP will select Non-Interspersed Parity mode.

A HIGH will select Interspersed Parity mode. The IP bit function allows the user

to select the parity bit in the long word loaded into the parallel port (D0-Dn) when

programming the flag offsets. If Interspersed Parity mode is selected, then the

FIFO will assume that the parity bits are located in bit position D8, D17, D26, D35,

D44, D53, D62 and D71 during the parallel programming of the flag offsets. If

Non-Interspersed Parity mode is selected, then D

8, D17 and D28 are is assumed

to be valid bits and D

64, D65, D66, D67, D68, D69, D70 and D71 are ignored.

IP mode is selected during Master Reset by the state of the IP input pin.

OUTPUTS:

FULL FLAG ( FF/IR )

This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function

is selected. When the FIFO is full, FF will go LOW, inhibiting further write

operations. When FF is HIGH, the FIFO is not full. If no reads are performed

after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO

(D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the

IDT72V7250, 4,096 for the IDT72V7260, 8,192 for the IDT72V7270, 16,384

for the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the

IDT72V72100). See Figure10, Write Cycle and Full Flag Timing (IDT

Standard Mode), for the relevant timing information.

In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW

when memory space is available for writing in data. When there is no longer

any free space left, IR goes HIGH, inhibiting further write operations. If no reads

are performed after a reset (either MRS or PRS), IR will go HIGH after D writes

to the FIFO (D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049

for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270,

16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the

IDT72V72100). See Figure 13, Write Timing (FWFT Mode), for the relevant

timing information.

The IR status not only measures the contents of the FIFO memory, but also

counts the presence of a word in the output register. Thus, in FWFT mode, the

total number of writes necessary to deassert IR is one greater than needed to

assert FF in IDT Standard mode.

FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are

double register-buffered outputs.

EMPTY FLAG ( EF/OR )

This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)

function is selected. When the FIFO is empty, EF will go LOW, inhibiting further

read operations. When EF is HIGH, the FIFO is not empty. See Figure 11,

Read Cycle, Output Enable, Empty Flag and First Word Latency Timing (IDT

Standard Mode), for the relevant timing information.

In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW

at the same time that the first word written to an empty FIFO appears valid on

the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts

the last word from the FIFO memory to the outputs. OR goes HIGH only with

a true read (RCLK with REN = LOW). The previous data stays at the outputs,

indicating the last word was read. Further data reads are inhibited until OR goes

LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing

information.

EF/OR is synchronous and updated on the rising edge of RCLK.

In IDT Standard mode, EF is a double register-buffered output. In FWFT

mode, OR is a triple register-buffered output.

PROGRAMMABLE ALMOST-FULL FLAG ( PAF )

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO

reaches the almost-full condition. In IDT Standard mode, if no reads are

performed after reset (MRS), PAF will go LOW after (D - m) words are written

to the FIFO. The PAF will go LOW after (512-m) writes for the IDT72V7230,

(1,024-m) writes for the IDT72V7240, (2,048-m) writes for the IDT72V7250,

(4,096-m) writes for the IDT72V7260, (8,192-m) writes for the IDT72V7270,

(16,384-m) writes for the IDT72V7280, (32,768-m) writes for the IDT72V7290,

and (65,536-m) writes for the IDT72V72100. The offset “m” is the full offset value.

The default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the PAF will go LOW after (513-m) writes for the IDT72V7230,

(1,025-m) writes for the IDT72V7240, (2,049-m) writes for the IDT72V7250,

(4,097-m) writes for the IDT72V7260 and (8,193-m) writes for the IDT72V7270,

(16,385-m) writes for the IDT72V7280, (32,769-m) writes for the IDT72V7290

and (65,537-m) writes for the IDT72V72100, where “m” is the full offset value.

The default setting for this value is stated in Table 2.

See Figure 23, Synchronous Programmable Almost-Full Flag Timing (IDT

Standard and FWFT Modes), for the relevant timing information.

If asynchronous PAF configuration is selected, the PAF is asserted LOW

on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH

on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF

configuration is selected, the PAF is updated on the rising edge of WCLK. See

Figure 25, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT

Modes).

PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE )

The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO

reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW

when there are n words or less in the FIFO. The offset “n” is the empty offset

value. The default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the PAE will go LOW when there are n+1 words or less

in the FIFO. The default setting for this value is stated in Table 2.

See Figure 24, Synchronous Programmable Almost-Empty Flag Timing

(IDT Standard and FWFT Modes), for the relevant timing information.

If asynchronous PAE configuration is selected, the PAE is asserted LOW

on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH

on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE

configuration is selected, the PAE is updated on the rising edge of RCLK. See

Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT

Standard and FWFT Modes).

HALF-FULL FLAG ( HF )

This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO

beyond half-full sets HF LOW. The flag remains LOW until the difference between

the write and read pointers becomes less than or equal to half of the total depth

of the device; the rising RCLK edge that accomplishes this condition sets HF

HIGH.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

IDT72V72100L10BB

Mfr. #:

Buy IDT72V72100L10BB

Manufacturer:

Description:

IC FIFO 131KX36 10NS 256BGA

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

IDT72V72100L10BB

IDT72V72100L10BB

Products related to this Datasheet