36
COMMERCIAL TEMPERATURE RANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
t
RTS
t
ENH
4680 drw24
t
ENS
W
x
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
0
- Q
n
t
SKEW2
12
1
t
PAFS
t
HF
t
PAES
W
x+1
2
W
3
WEN
t
ENS
W
2
(4)
4
5
t
ENH
W
4
t
A
t
A
t
A
W
5
t
A
(4)
(4)
3
t
A
W1
SCLK
SEN
SI
4680 drw25
tENH
t
ENS
tLDS
LD
tDS
BIT 0
EMPTY OFFSET
BIT X
BIT 0
FULL OFFSET
(1)
t
ENH
BIT X
(1)
tLDH
tDH
tLDH
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. X = 9 for the IDT72V7230, X= 10 for the IDT72V7240, X = 11 for the IDT72V7250, X = 12 for the IDT72V7260, X = 13 for the IDT72V7270, X = 14 for the IDT72V7280,
X = 15 for the IDT72V7290 and X = 16 for the IDT72V72100.
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280, 32,769 for
the IDT72V7290 and 65,537 for the IDT72V72100.
3. OE = LOW; RCS = LOW.
4. W
1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 19. Zero Latency Retransmit Timing (FWFT Mode)
