38
COMMERCIAL TEMPERATURE RANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
WCLK
tENH
tCLKH
tCLKL
WEN
PAE
RCLK
tENS
n words in FIFO
(2)
,
n+1 words in FIFO
(3)
tPAES
tSKEW2
tPAES
12 12
(4)
REN
4680 drw29
tENS
tENH
n+1 words in FIFO
(2)
,
n+2 words in FIFO
(3)
n words in FIFO
(2)
,
n+1 words in FIFO
(3)
WCLK
t
CLKH
t
CLKL
t
ENS
t
ENH
WEN
PAF
t
ENS
t
PAFA
D - (m + 1) words
in FIFO
RCLK
t
PAFA
REN
4680 drw30
D - m words
in FIFO
D - (m + 1) words in FIFO
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4.
tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS is LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode:
D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250, 4,096 for the IDT72V7260, 8,192 for the IDT72V7270, 16,384 for the
IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
In FWFT Mode: D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280,
32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
