OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

IDT72V72100L10BB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
31
COMMERCIAL TEMPERATURE RANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
WCLK
12
WEN
D
0
- D
n
RCLK
t
ENS
REN
Q
0
- Q
n
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
t
OHZ
t
SKEW1
t
ENH
t
DS
t
DH
t
OE
t
A
t
A
t
A
t
PAFS
t
WFF
t
WFF
t
ENS
OE
t
SKEW2
W
D
4680 drw 19
t
PAES
W
[D-n]
W
[D-n-1]
t
A
t
A
t
HF
t
REF
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
t
ENS
D-1
][
W
D-1
][
W
1
Figure 14. Read Timing (First Word Fall Through Mode)
NOTES:
1. t
SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 513 for IDT72V7230, 1,025 for IDT72V7240, 2,049 for IDT72V7250, 4,097 for IDT72V7260, 8,193 for IDT72V7270, 16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
6. RCS = LOW.
32
COMMERCIAL TEMPERATURE RANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
WCLK
12
WEN
D
0 - Dn
RCLK
REN
Q
0 - Qn
PAF
HF
PAE
IR
OR
W
1
W
2
W
3
W
m+2
W
[m+3]
t
RCSHZ
t
SKEW1
t
ENH
t
DS
t
DH
t
A
t
A
t
PAFS
t
WFF
t
WFF
t
ENS
RCS
t
SKEW2
W
D
4680 drw 20
t
PAES
W
[D-n]
W
[D-n-1]
t
A
t
A
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
t
ENS
1
t
RCSS
t
RCSLZ
t
ENS
t
HF
t
REF
D-1
][
W
D-1
][
W
t
RCSH
Figure 15. Read Cycle and Read Chip Select Timing (First Word Fall Through Mode)
NOTES:
1. t
SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 513 for IDT72V7230, 1,025 for IDT72V7240, 2,049 for IDT72V7250, 4,097 for IDT72V7260, 8,193 for IDT72V7270, 16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
6. OE = LOW.
33
COMMERCIAL TEMPERATURE RANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
t
REF
t
RTS
t
ENH
4680 drw21
t
A
t
ENS
W
x
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q
0
- Q
n
t
SKEW2
12
1
W
1
t
PAFS
t
HF
t
PAES
t
REF
W
x+1
2
W
2
t
ENH
WEN
t
ENS
t
RTS
t
ENS
t
ENH
(3)
t
A
t
A
(3)
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW; RCS = LOW.
3. W
1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 512 for IDT72V7230, 1,024 for IDT72V7240, 2,048 for IDT72V7250, 4,096 for IDT72V7260, 8,192 for IDT72V7270, 16,384 for the IDT72V7280, 32,768 for the IDT72V7290
and 65,536 for the IDT72V72100.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 16. Retransmit Timing (IDT Standard Mode)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

IDT72V72100L10BB

Mfr. #:
Buy IDT72V72100L10BB
Manufacturer:
Description:
IC FIFO 131KX36 10NS 256BGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet