24
COMMERCIAL TEMPERATURE RANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
Test-Logic
Reset
Run-Test/
Idle
1
0
0
Select-
DR-Scan
Select-
IR-Scan
1
1
1
Capture-IR
0
Capture-DR
0
0
EXit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
1
0
1
1
1
4680 drw12
0
Shift-DR
0
0
0
Shift-IR
0
0
Pause-IR
0
1
Input = TMS
0
01
Figure 7. TAP Controller State Diagram
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
CAPTURE-DR
Data is loaded from the parallel input pins or core outputs into the Data
Register.
SHIFT-DR
The previously captured data is shifted in serially, LSB first at the rising edge
of TCLK in the TDI/TDO path and shifted out serially, LSB first at the falling edge
of TCLK towards the output.
UPDATE-DR
The shifting process has been completed. The data is latched into their
parallel outputs in this state to be accessed through the internal bus.
EXIT1-DR / EXIT2-DR
This is a temporary controller state. If TMS is held high, a rising edge applied
to TCK while in this state causes the controller to enter the Update-DR state. This
terminates the scanning process. All test data registers selected by the current
instruction retain their previous state unchanged.
PAUSE-DR
This controller state allows shifting of the test data register in the serial path
between TDI and TDO to be temporarily halted. All test data registers selected
by the current instruction retain their previous state unchanged.
Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are
similar to Data registers. These instructions operate on the instruction registers.
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
