19
COMMERCIAL TEMPERATURE RANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC II
TM
FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 512 for the
IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250, 4,096 for
the IDT72V7260, 8,192 for the IDT72V7270, 16,384 for the IDT72V7280,
32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 513 for the
IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for
the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280,
32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
0-Qn)
(Q0-Q71) are data outputs for 72-bit wide data, (Q0 - Q35) are data outputs
for 36-bit wide data or (Q0-Q17) are data outputs for 18-bit wide data.
