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AD73360
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PIN FUNCTION DESCRIPTION
Mnemonic Function
VINP1 Analog Input to the Positive Terminal of Input Channel 1.
VINN1 Analog Input to the Negative Terminal of Input Channel 1.
VINP2 Analog Input to the Positive Terminal of Input Channel 2.
VINN2 Analog Input to the Negative Terminal of Input Channel 2.
VINP3 Analog Input to the Positive Terminal of Input Channel 3.
VINN3 Analog Input to the Negative Terminal of Input Channel 3.
VINP4 Analog Input to the Positive Terminal of Input Channel 4.
VINN4 Analog Input to the Negative Terminal of Input Channel 4.
VINP5 Analog Input to the Positive Terminal of Input Channel 5.
VINN5 Analog Input to the Negative Terminal of Input Channel 5.
VINP6 Analog Input to the Positive Terminal of Input Channel 6.
VINN6 Analog Input to the Negative Terminal of Input Channel 6.
REFOUT Buffered Reference Output, which has a nominal value of 1.25 V or 2.5 V, the value being dependent on the status
of Bit 5VEN (CRC:7).
REFCAP A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to
this pin. This pin can be overdriven by an external reference if required.
AVDD2 Analog Power Supply Connection.
AGND2 Analog Ground/Substrate Connection.
DGND Digital Ground/Substrate Connection.
DVDD Digital Power Supply Connection.
RESET Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital
circuitry.
SCLK Output Serial Clock whose rate determines the serial transfer rate to/from the AD73360. It is used to clock data or
control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the
master clock (MCLK) divided by an integer numberthis integer number being the product of the external mas-
ter clock rate divider and the serial clock rate divider.
MCLK Master Clock Input. MCLK is driven from an external clock signal.
SDO Serial Data Output of the AD73360. Both data and control information may be output on this pin and are clocked
on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is
low.
SDOFS Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period
before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in
three-state when SE is low.
SDIFS Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period
before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored
when SE is low.
SDI Serial Data Input of the AD73360. Both data and control information may be input on this pin and are clocked on
the negative edge of SCLK. SDI is ignored when SE is low.
SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease
power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values
(before SE was brought low); however, the timing counters and other internal registers are at their reset values.
AGND1 Analog Ground Connection.
AVDD1 Analog Power Supply Connection.
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AD73360
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TERMINOLOGY
Absolute Gain
Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for each ADC. The absolute gain specification
is used for gain tracking error specification.
Crosstalk
Crosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.
Gain Tracking Error
Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB by
definition.
Group Delay
Group Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the de-
gree of nonlinear phase response of the system.
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 0 Hz4 kHz).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa fb), while the third order
terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which each ADC updates its out-
put register. It is set relative to the DMCLK and the program-
mable sample rate setting.
SNR + THD
Signal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in a given frequency
range, including harmonics but excluding dc.
ABBREVIATIONS
ADC Analog-to-Digital Converter.
BW Bandwidth.
CRx A Control Register where x is a placeholder for
an alphabetic character (AE). There are eight
read/write control registers on the AD73360
designated CRA through CRE.
CRx:n A bit position, where n is a placeholder for a
numeric character (07), within a control regis-
ter; where x is a placeholder for an alphabetic
character (AE). Position 7 represents the MSB
and Position 0 represents the LSB.
DMCLK Device (Internal) Master Clock. This is the
internal master clock resulting from the external
master clock (MCLK) being divided by the on-
chip master clock divider.
FSLB Frame Sync Loop-Backwhere the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of first
device in the cascade. Data input and output
occur simultaneously. In the case of nonFSLB,
SDOFS and SDO are connected to the Rx Port
of the DSP while SDIFS and SDI are connected
to the Tx Port.
PGA Programmable Gain Amplifier.
SC Switched Capacitor.
SNR Signal-to-Noise Ratio.
SPORT Serial Port.
THD Total Harmonic Distortion.
VBW Voice Bandwidth.
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AD73360
11
FUNCTIONAL DESCRIPTION
General Description
The AD73360 is a six-channel, 16-bit, analog front end. It
comprises six independent encoder channels each featuring
signal conditioning, programmable gain amplifier, sigma-delta
A/D convertor and decimator sections. Each of these sections is
described in further detail below.
Encoder Channel
Each encoder channel consists of a signal conditioner, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input
antialias requirements are reduced such that a simple single pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
Signal Conditioner
Each analog channel has an independent signal conditioning
block. This allows the analog input to be configured by the user
depending on whether differential or single-ended mode is used.
Programmable Gain Amplifier
Each encoder sections analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modula-
tor. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 in control
Registers D, E and F.
Table IV. PGA Settings for the Encoder Channel
IxGS2 IxGS1 IxGS0 Gain (dB)
000 0
001 6
010 12
011 18
100 20
101 26
110 32
111 38
ADC
Each channel has its own ADC consisting of an analog sigma-
delta modulator and a digital antialiasing decimation filter. The
sigma-delta modulator noise-shapes the signal and produces
1-bit samples at a DMCLK/8 rate. This bitstream, representing
the analog input signal, is input to the antialiasing decimation
filter. The decimation filter reduces the sample rate and in-
creases the resolution.
Analog Sigma-Delta Modulator
The AD73360 input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73360, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to f
S
/2 = DMCLK/16
(Figure 6a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 6b). The combina-
tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 6c).
BAND
OF
INTEREST
F
S
/2
DMCLK/16
F
S
/2
DMCLK/16
F
S
/2
DMCLK/16
DIGITAL FILTER
NOISE-SHAPING
BAND
OF
INTEREST
BAND
OF
INTEREST
a.
b.
c.
Figure 6. Sigma-Delta Noise Reduction

AD73360ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE IC 6-CH AFE Processor
Lifecycle:
New from this manufacturer.
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