AD73360ARZ Datasheet AD73360ARZ, AD73360ASUZ, AD73360LARZ | P19-P21

REV. B

AD73360

–18–

Control Register C

CRC:0 Global Power-Up. Writing a 1 to this bit will cause all six channels of the AD73360 to power-up regardless of the

status of the Power Control Bits in CRD-CRF. If less than six channels are required, this bit should be set to 0 and

the Power Control Bits of the relevant channels should be set to 1.

CRC:1–4 Reserved. These bits are reserved and should be programmed to 0 to ensure correct operation.

CRC:5 Power-Up Reference. This bit controls the state of the on-chip reference. A 1 in this bit will power up the refer-

ence. A 0 in this bit will power-down the reference. Note that the reference is automatically powered up if any

channel is enabled.

CRC:6 Reference Output. When this bit is set to 1, the REFOUT pin is enabled.

CRC:7 5 V Enable. When this bit is set to 1, the 5 V operating mode is enabled.

Control Register D

CRD:0–2 Input Gain Selection. These bits select the input gain for ADC1. See Table IV.

CRD:3 Power Control for ADC1. A 1 in this bit powers up ADC1.

CRD:4–6 Input Gain Selection. These bits select the input gain for ADC2. See Table IV.

CRD:7 Power Control for ADC2. A 1 in this bit powers up ADC2.

Control Register E

CRE:0-2 Input Gain Selection. These bits select the input gain for ADC3. See Table IV.

CRE:3 Power Control for ADC3. A 1 in this bit powers up ADC3.

CRE:4–6 Input Gain Selection. These bits select the input gain for ADC4. See Table IV.

CRE:7 Power Control for ADC4. A 1 in this bit powers up ADC4.

Control Register F

CRF:0–2 Input Gain Selection. These bits select the input gain for ADC5. See Table IV.

CRF:3 Power Control for ADC5. A 1 in this bit powers up ADC5.

CRF:4–6 Input Gain Selection. These bits select the input gain for ADC6. See Table IV.

CRF:7 Power Control for ADC6. A 1 in this bit powers up ADC6.

Control Register G

CRG:0–5 Channel Select. These bits are used in association with CRG:6 and CRG:7. If the Reset Analog Modulator bit

(CRG:6) is 1, then a 1 in a Channel Select bit location will reset the Analog Modulator for that channel. If the

Single-Ended Enable Mode bit (CRG:7) is 1, then a 1 in a Channel Select bit location will put that channel into

Single-Ended Mode. If any channel has its Channel Select bit set to 0, the channel will be set for Differentially-

Ended Mode and will not have its analog modulator reset regardless of the state of CRG:6 and CRG:7.

CRG:6 Reset Analog Modulator. Setting this bit to a 1 will reset the Analog Modulators for any channel whose Channel

Select bit (CRG:0–5) is set to 1. This bit should be set to 0 for normal operation.

CRG:7 Single-Ended Enable Mode. Setting this bit to a 1 will enable Single-Ended Mode on any channel whose Channel

Select bit (CRG:0–5) is set to 1. Setting this bit to 0 will select Differentially-Ended Input Mode for all channels.

Control Register H

CRH:0–5 Invert Select. These bits are used in association with CRH:7. If the Enable Invert Channel Mode bit (CRH:7) is 1,

then a 1 in a Channel Select bit location will put that channel into Inverted Mode. If any channel has its Channel

Select bit set to 0, the channel will not be inverted regardless of the state CRH:7.

CRH:6 Test Mode Enable. This bit should be set to 0 to ensure normal operation.

CRH:7 Enable Invert Channel Mode. Setting this bit to a 1 will enable invert any channel whose Channel Select bit

(CRH:0–5) is set to 1. Setting this bit to 0 will select Noninverted (Normal) Mode for all channels.

REV. B

AD73360

–19–

Master Clock Divider

The AD73360 features a programmable master clock divider

that allows the user to reduce an externally available master

clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to pro-

duce an internal master clock signal (DMCLK) that is used to

calculate the sampling and serial clock rates. The master clock

divider is programmable by setting CRB:4-6. Table XV shows

the division ratio corresponding to the various bit settings. The

default divider ratio is divide-by-one.

Table XV. DMCLK (Internal) Rate Divider Settings

MCD2 MCD1 MCD0 DMCLK Rate

0 0 0 MCLK

0 0 1 MCLK/2

0 1 0 MCLK/3

0 1 1 MCLK/4

1 0 0 MCLK/5

1 0 1 MCLK

1 1 0 MCLK

1 1 1 MCLK

Serial Clock Rate Divider

The AD73360 features a programmable serial clock divider that

allows users to match the serial clock (SCLK) rate of the data to

that of the DSP engine or host processor. The maximum SCLK

rate available is DMCLK and the other available rates are:

DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate

(DMCLK/8) is the default SCLK rate. The serial clock divider

is programmable by setting bits CRB:2–3. Table XVI shows the

serial clock rate corresponding to the various bit settings.

Table XVI. SCLK Rate Divider Settings

SCD1 SCD0 SCLK Rate

0 0 DMCLK/8

0 1 DMCLK/4

1 0 DMCLK/2

1 1 DMCLK

Decimation Rate Divider

The AD73360 features a programmable decimation rate divider

that allows users flexibility in matching the AD73360’s ADC

sample rates to the needs of the DSP software. The maximum

sample rate available is DMCLK/256 and the other available

rates are: DMCLK/512, DMCLK/1024 and DMCLK/2048.

The slowest rate (DMCLK/2048) is the default sample rate.

The sample rate divider is programmable by setting bits CRB:0-1.

Table XVII shows the sample rate corresponding to the various

bit settings.

Table XVII. Decimation Rate Divider Settings

DR1 DR0 Sample Rate

0 0 DMCLK/2048

0 1 DMCLK/1024

1 0 DMCLK/512

1 1 DMCLK/256

OPERATION

General Description

The AD73360 inputs and outputs data in a Time Division

Multiplexing (TDM) format. When data is being read from the

AD73360 each channel has a fixed time slot in which its data is

transmitted. If a channel is not powered up, no data is transmit-

ted during the allocated time slot and the SDO line will be

three-stated. When the AD73360 is first powered up or reset it

will be set to Program Mode and will output an SDOFS. After a

reset the SDOFS will be asserted once every sample period

(125 µs assuming 16.384 MHz master clock). If the AD73360 is

configured in Frame Sync Loop-Back Mode, one control word

can be transmitted after each SDOFS pulse. Figure 10a shows

the SDO and SDOFS lines after a reset. The serial data sent by

SDO will not contain valid ADC data until the AD73360 is put

into Data Mode or Mixed Mode. Control Registers D through

F allow channels to be powered up individually. This gives

greater flexibility and control over power consumption. Figure

10b shows the SDOFS and SDO of the AD73360 when all

channels are powered up and Figure 10c shows SDOFS and

SDO with channels 1, 3 and 5 powered up.

SDOFS

SDO

1/F

SAMPLE

Figure 10a. Output Timing After Reset (Program Mode)

SDOFS

SDO

CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6

Figure 10b. Output Timing: All Channels Powered Up (Data/Mixed Mode)

SDOFS

SDO

CHANNEL 5CHANNEL 1

CHANNEL 3

Figure 10c. Output Timing: Channels 1, 3 and 5 Powered Up (Data/Mixed Mode)

REV. B

AD73360

–20–

Resetting the AD73360

The RESET pin resets all the control registers. All registers are

reset to zero indicating that the default SCLK rate (DMCLK/8)

and sample rate (DMCLK/2048) are at a minimum to ensure

that slow speed DSP engines can communicate effectively. As

well as resetting the control registers using the RESET pin, the

device can be reset using the RESET bit (CRA:7) in Control

DMCLK cycles. On reset, DATA/PGM (CRA:0) is set to 0

(default condition) thus enabling Program Mode. The reset

conditions ensure that the device must be programmed to the

correct settings after power-up or reset. Following a reset, the

SDOFS will be asserted approximately 2070 master (MCLK)

cycles after RESET goes high. The data that is output following

the reset and during Program Mode is random and contains no

valid information until either data or mixed mode is set.

Power Management

The individual functional blocks of the AD73360 can be en-

abled separately by programming the power control register

CRC. It allows certain sections to be powered down if not re-

quired, which adds to the device’s flexibility in that the user

need not incur the penalty of having to provide power for a

certain section if it is not necessary to their design. The power

control registers provide individual control settings for the major

functional blocks on each analog front end unit and also a global

override that allows all sections to be powered up/down by

setting/clearing the bit. Using this method the user could, for

example, individually enable a certain section, such as the refer-

ence (CRC:5), and disable all others. The global power-up

(CRC:0) can be used to enable all sections but if power-down is

required using the global control, the reference will still be en-

abled; in this case, because its individual bit is set. Refer to

Table XII for details of the settings of CRC. CRD–CRF can be

used to control the power status of individual channels allowing

multiple channels to be powered down if required.

Operating Modes

There are three operating modes available on the AD73360.

They are Program, Data and Mixed Program/Data. The device

configuration—register settings—can be changed only in Pro-

gram and Mixed Program/Data Modes. In all modes, transfers

of information to or from the device occur in 16-bit packets,

therefore the DSP engine’s SPORT will be programmed for 16-

bit transfers.

Program (Control) Mode

In Program Mode, CRA:0 = 0, the user writes to the control

registers to set up the device for desired operation—SPORT

operation, cascade length, power management, input/output

gain, etc. In this mode, the 16-bit information packet sent to the

device by the DSP engine is interpreted as a control word whose

format is shown in Table VI. In this mode, the user must ad-

dress the device to be programmed using the address field of the

control word. This field is read by the device and if it is zero

(000 bin), the device recognizes the word as being addressed to it.

If the address field is not zero, it is then decremented and the

control word is passed out of the device—either to the next

device in a cascade or back to the DSP engine. This 3-bit ad-

dress format allows the user to uniquely address any one of up

to eight devices in a cascade. If the AD73360 is used in a stand-

alone configuration connected to a DSP, the device address

corresponds to 0. If, on the other hand, the AD73360 is config-

ured in a cascade of multiple devices, its device address corre-

sponds with its hardwired position in the cascade.

Following reset, when the SE pin is enabled, the AD73360

responds by raising the SDOFS pin to indicate that an output

sample event has occurred. Control words can be written to the

device to coincide with the data being sent out of the SPORT, as

shown in Figure 12 (Directly Coupled), or they can lag the out-

put words by a time interval that should not exceed the sample

interval (Indirectly Coupled). Refer to the Digital Interface

section for more information. After reset, output frame sync

pulses will occur at a slower default sample rate, which is DM-

CLK/2048, until Control Register B is programmed, after which

the SDOFS will be pulsed at the selected rate. This is to allow

slow controller devices to establish communication with the

AD73360. During Program Mode, the data output by the de-

vice is random and should not be interpreted as ADC data.

Data Mode

Once the device has been configured by programming the cor-

rect settings to the various control registers, the device may exit

Program Mode and enter Data Mode. This is done by program-

ming the DATA/PGM (CRA:0) bit to a 1 and MM (CRA:1) to

0. Once the device is in Data Mode, the input data is ignored.

When the device is in normal Data Mode (i.e., mixed mode

disabled), it must receive a hardware reset to reprogram any of

the control register settings.

Appendix C details the initialization and operation of an analog

front end cascade in normal Data Mode.

Mixed Program/Data Mode

This mode allows the user to send control words to the device

while receiving ADC words. This permits adaptive control of

the device whereby control of the input gains can be affected by

reprogramming the control registers. The standard data frame

remains 16 bits, but now the MSB is used as a flag bit to indi-

cate that the remaining 15 bits of the frame represents control

information. Mixed mode is enabled by setting the MM bit

(CRA:1) to 1 and the DATA/PGM bit (CRA:0) to 1. In the

case where control setting changes will be required during nor-

mal operation, this mode allows the ability to load control infor-

mation with the slight inconvenience of formatting the data.

Note that the output samples from the ADC will also have the

MSB set to zero to indicate it is a data word.

A description of a single device operating in mixed mode is

detailed in Appendix B, while Appendix D details the initializa-

tion and operation of an analog front end cascade operating in

mixed mode. Note that it is not essential to load the control

registers in Program Mode before setting mixed mode active.

Mixed mode may be selected with the first write by program-

ming CRA and then transmitting other control words.

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AD73360ARZ

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Analog Front End - AFE IC 6-CH AFE Processor

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AD73360ARZ

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