REV. B
AD73360
21
INTERFACING
The AD73360 can be interfaced to most modern DSP engines
using conventional serial port connections and an extra enable
control line. Both serial input and output data use an accompa-
nying frame synchronization signal which is active high one
clock cycle before the start of the 16-bit word or during the last
bit of the previous word if transmission is continuous. The serial
clock (SCLK) is an output from the AD73360 and is used to
define the serial transfer rate to the DSPs Tx and Rx ports.
Two primary configurations can be used: the first is shown in
Figure 11 where the DSPs Tx data, Tx frame sync, Rx data and
Rx frame sync are connected to the AD73360s SDI, SDIFS,
SDO and SDOFS respectively. This configuration, referred to
as indirectly coupled or nonframe sync loop-back, has the effect
of decoupling the transmission of input data from the receipt of
output data. When programming the DSP serial port for this
configuration, it is necessary to set the Rx frame sync as an
input to the DSP and the Tx frame sync as an output generated
by the DSP. This configuration is most useful when operating in
mixed mode, as the DSP has the ability to decide how many
words can be sent to the AD73360(s). This means that full con-
trol can be implemented over the device configuration in a given
sample interval. The second configuration (shown in Figure 12)
has the DSPs Tx data and Rx data connected to the AD73360s
SDI and SDO, respectively, while the DSPs Tx and Rx frame
syncs are connected to the AD73360s SDIFS and SDOFS. In
this configuration, referred to as directly coupled or frame sync
loop-back, the frame sync signals are connected together and
the input data to the AD73360 is forced to be synchronous with
the output data from the AD73360. The DSP must be pro-
grammed so that both the Tx and Rx frame syncs are inputs as
the AD73360s SDOFS will be input to both. This configura-
tion guarantees that input and output events occur simulta-
neously and is the simplest configuration for operation in normal
Data Mode. Note that when programming the DSP in this
configuration it is advisable to preload the Tx register with the
first control word to be sent before the AD73360 is taken out of
reset. This ensures that this word will be transmitted to coincide
with the first output word from the device(s).
Digital Interfacing
The AD73360 is designed to easily interface to most common
DSPs. The SCLK, SDO, SDOFS, SDI and SDIFS must be
connected to the SCLK, DR, RFS, DT and TFS pins of the
DSP respectively. The SE pin may be controlled from a parallel
output pin or flag pin such as FL02 on the ADSP-21xx (or XF
on the TMS320C5x) or, where SPORT power-down is not
required, it can be permanently strapped high using a suitable
pull-up resistor. The RESET pin may be connected to the sys-
tem hardware reset structure or it may also be controlled using a
dedicated control line. In the event of tying it to the global
system reset, it is necessary to operate the device in mixed
mode, which allows a software reset, otherwise there is no con-
venient way of resetting the device. Figures 11 and 12 show
typical connections to an ADSP-2181 while Figures 13 and 14
show typical connections to an ADSP-21xx and a TMS320C5x,
respectively.
TFS
DT
SCLK
DR
RFS
ADSP-21xx
DSP
AD73360
SDIFS
SDI
SCLK
SDO
SDOFS
Figure 11. Indirectly Coupled or Nonframe Sync Loop-
Back Configuration
TFS
DT
SCLK
DR
RFS
ADSP-21xx
DSP
AD73360
SDIFS
SDI
SCLK
SDO
SDOFS
Figure 12. Directly Coupled or Frame Sync Loop-
Back Configuration
TFS
DT
SCLK
DR
RFS
ADSP-21xx
DSP
AD73360
ANALOG
FRONT-END
SDIFS
SDI
SCLK
SDO
SDOFS
FL0
FL1
RESET
SE
Figure 13. AD73360 Connected to ADSP-21xx
FSX
DX
CLKX
CLKR
DR
TMS320C5x
DSP
AD73360
ANALOG
FRONT-END
SDIFS
SDI
SCLK
SDO
SDOFS
FSR
XF
RESET
SE
Figure 14. AD73360 Connected to TMS320C5x
REV. B
AD73360
22
SE
SDI
CONTROL WORD
CONTROL WORD
SDIFS
UNDEFINED DATA
SDO
UNDEFINED DATA
SDOFS
SCLK
Figure 15a. Interface Signal Timing for Program Mode Operation (Writing to a Register)
SE
SCLK
SDIFS
SDI
REGISTER READ INSTRUCTION
0x7FFF OR CONTROL WORD
UNDEFINED DATA
SDO
READ RESULT
SDOFS
Figure 15b. Interface Signal Timing for Program Mode Operation (Reading a Register)
SE
SDOFS
SCLK
SDIFS
SDI
CONTROL WORD
CONTROL WORD
CHANNEL 1 ADC SAMPLE WORDSDO
CHANNEL 6 ADC SAMPLE WORD
Figure 16a. Interface Signal Timing for Mixed Mode Operation
SE
SDOFS
SCLK
SDIFS
SDI DON'T CARE
DON'T CARE
CHANNEL 1 ADC SAMPLE WORDSDO CHANNEL 6 ADC SAMPLE WORD
Figure 16b. Interface Signal Timing for Data Mode Operation
REV. B
AD73360
23
Cascade Operation
The AD73360 has been designed to support up to eight devices
in a cascade connected to a single serial port (see Figure 17).
The SPORT interface protocol has been designed so that device
addressing is built into the packet of information sent to the
device. This allows the cascade to be formed with no extra hard-
ware overhead for control signals or addressing. A cascade can
be formed in either of the two modes previously discussed.
TFS
DT
DR
RFS
AD73360
SDIFS
SDI
SCLK
SDO
SDOFS
SCLK
DEVICE 1
MCLK
SE
RESET
AD73360
74HC74
Q0
Q1
D1
D0
FL0 FL1
ADSP-2181
DSP
CLK
SDIFS
SDI
SCLK
SDO
SDOFS
DEVICE 2
MCLK
SE
RESET
Figure 17. Connection of Two AD73360s Cascaded to
ADSP-2181
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. The formula below gives an indication of whether
the combination of sample rate, serial clock and number of
devices can be successfully cascaded. This assumes a directly
coupled frame sync arrangement as shown in Figure 12 and does
not take any interrupt latency into account.
16 11617
f
Device Count
SCLK
S
×−×+[(( ) ) ]
When using the indirectly coupled frame sync configuration in
cascaded operation it is necessary to be aware of the restrictions
in sending control word data to all devices in the cascade. The
user should ensure that there is sufficient time for all the control
words to be sent between reading the last ADC sample and the
start of the next sample period.
In Cascade Mode, each device must know the number of de-
vices in the cascade to be able to output data at the correct
time. Control Register A contains a 3-bit field (DC02) that is
programmed by the DSP during the programming phase. The
default condition is that the field contains 000b, which is equiva-
lent to a single device in cascade (see Table XVIII). However,
for cascade operation this field must contain a binary value that
is one less than the number of devices in the cascade. With a
number of AD73360s in cascade each device takes a turn to
send an ADC result to the DSP. For example, in a cascade of
two devices the data will be output as Device 2-Channel 1,
Device 1-Channel 1, Device 2-Channel 2, Device 1-Channel 2
etc. When the first device in the cascade has transmitted its
channel data there is an additional SCLK period during which
the last device asserts its SDOFS as it begins its transmission of
the next channel. This will not cause a problem for most DSPs
as they count clock edges after a frame sync and hence the
extra bit will be ignored.
When multiple devices are connected in cascade there are also
restrictions concerning which ADC channels can be powered
up. In all cases the cascaded devices must all have the same
channels powered up (i.e., for a cascade of two devices requir-
ing Channels 1 and 2 on Device 1 and Channel 5 on Device 2,
Channels 1, 2 and 5 must be powered up on both devices to
ensure correct operation). Figure 18 shows the timing se-
quence for two devices in cascade.
Table XVIII. Device Count Settings
DC2 DC1 DC0 Cascade Length
00 01
00 12
01 03
01 14
10 05
10 16
11 07
11 18
Connection of a cascade of devices to a DSP, as shown in
Figure 17, is no more complicated than connecting a single
device. Instead of connecting the SDO and SDOFS to the
DSPs Rx port, these are now daisy-chained to the SDI and
SDIFS of the next device in the cascade. The SDO and
SDOFS of the final device in the cascade are connected to the
DSPs Rx port to complete the cascade. SE and RESET on all
devices are fed from the signals that were synchronized with
the MCLK using the circuit of Figure 19. The SCLK from
only one device need be connected to the DSPs SCLK input(s)
as all devices will be running at the same SCLK frequency and
phase.
12345678910111213141516123456 7891011121314151617
DEVICE 2 - CHANNEL 1
DEVICE 1 - CHANNEL 1
12345 67 8
DEVICE 2 - CHANNEL 2
Figure 18. Cascade Timing for a Two-Device Cascade

AD73360ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE IC 6-CH AFE Processor
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