AD73360ARZ Datasheet AD73360ARZ, AD73360ASUZ, AD73360LARZ | P16-P18

REV. B

AD73360

–15–

Table VII. Control Register A Description

7 654321 0

RESET DC2 DC1 DC0 SLB – MM DATA/PGM

Bit Name Description

0 DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)

1 MM Mixed Mode (0 = OFF; 1 = Enabled)

2 Reserved Must Be Programmed to Zero (0)

3 SLB SPORT Loop-Back Mode (0 = OFF; 1 = Enabled)

4 DC0 Device Count (Bit 0)

5 DC1 Device Count (Bit 1)

6 DC2 Device Count (Bit 2)

7 RESET Software Reset (0 = OFF; 1 = Initiates Reset)

Table VIII. Control Register B Description

76543210

C E E MCD2 MCD1 MCD0 SCD1 SCD0 DR1 DR0

Bit Name Description

0 DR0 Decimation Rate (Bit 0)

1 DR1 Decimation Rate (Bit 1)

2 SCD0 Serial Clock Divider (Bit 0)

3 SCD1 Serial Clock Divider (Bit 1)

4 MCD0 Master Clock Divider (Bit 0)

5 MCD1 Master Clock Divider (Bit 1)

6 MCD2 Master Clock Divider (Bit 2)

7 CEE Control Echo Enable (0 = OFF; 1 = Enabled)

Table IX. Control Register C Description

76543210

5VEN RU PUREF ––––GPU

Bit Name Description

0 GPU Global Power-Up Device (0 = Power Down; 1 = Power Up)

1 Reserved Must Be Programmed to Zero (0)

2 Reserved Must Be Programmed to Zero (0)

3 Reserved Must Be Programmed to Zero (0)

4 Reserved Must Be Programmed to Zero (0)

5 PUREF REF Power (0 = Power Down; 1 = Power Up)

6 RU REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)

7 5VEN Enable 5 V Operating Mode (0 = Disable 5 V Mode;

1 = Enable 5 V Mode)

CONTROL REGISTER A

CONTROL REGISTER B

CONTROL REGISTER C

REV. B

AD73360

–16–

Table X. Control Register D Description

76543210

PUI2 I2GS2 I2GS1 I2GS0 PUI1 I1GS2 I1GS1 I1GS0

Bit Name Description

0 I1GS0 ADC1:Input Gain Select (Bit 0)

1 I1GS1 ADC1:Input Gain Select (Bit 1)

2 I1GS2 ADC1:Input Gain Select (Bit 2)

3 PUI1 Power Control (ADC1); 1 = ON, 0 = OFF

4 I2GS0 ADC2:Input Gain Select (Bit 0)

5 I2GS1 ADC2:Input Gain Select (Bit 1)

6 I2GS2 ADC2:Input Gain Select (Bit 2)

7 PUI2 Power Control (ADC2); 1 = ON, 0 = OFF

Table XI. Control Register E Description

76543210

PUI4 I4GS2 I4GS1 I4GS0 PUI3 I3GS2 I3GS1 I3GS0

Bit Name Description

0 I3GS0 ADC3:Input Gain Select (Bit 0)

1 I3GS1 ADC3:Input Gain Select (Bit 1)

2 I3GS2 ADC3:Input Gain Select (Bit 2)

3 PUI3 Power Control (ADC3); 1 = ON, 0 = OFF

4 I4GS0 ADC4:Input Gain Select (Bit 0)

5 I4GS1 ADC4:Input Gain Select (Bit 1)

6 I4GS2 ADC4:Input Gain Select (Bit 2)

7 PUI4 Power Control (ADC4); 1 = ON, 0 = OFF

Table XII. Control Register F Description

76543210

PUI6 I6GS2 I6GS1 I6GS0 PUI5 I5GS2 I5GS1 I5GS0

Bit Name Description

0 I5GS0 ADC5:Input Gain Select (Bit 0)

1 I5GS1 ADC5:Input Gain Select (Bit 1)

2 I5GS2 ADC5:Input Gain Select (Bit 2)

3 PUI5 Power Control (ADC5); 1 = ON, 0 = OFF

4 I6GS0 ADC6:Input Gain Select (Bit 0)

5 I6GS1 ADC6:Input Gain Select (Bit 1)

6 I6GS2 ADC6:Input Gain Select (Bit 2)

7 PUI6 Power Control (ADC6); 1 = ON, 0 = OFF

CONTROL REGISTER D

CONTROL REGISTER E

CONTROL REGISTER F

REV. B

AD73360

–17–

Table XIII. Control Register G Description

76543210

SEEN RMOD CH6 CH5 CH4 CH3 CH2 CH1

Bit Name Description

0 CH1 Channel 1 Select

1 CH2 Channel 2 Select

2 CH3 Channel 3 Select

3 CH4 Channel 4 Select

4 CH5 Channel 5 Select

5 CH6 Channel 6 Select

6 RMOD Reset Analog Modulator

7 SEEN Enable Single-Ended Input Mode

Table XIV. Control Register H Description

76543210

INV TME CH6 CH5 CH4 CH3 CH2 CH1

Bit Name Description

0 CH1 Channel 1 Select

1 CH2 Channel 2 Select

2 CH3 Channel 3 Select

3 CH4 Channel 4 Select

4 CH5 Channel 5 Select

5 CH6 Channel 6 Select

6 TME Test Mode Enable

7 INV Enable Invert Channel Mode

CONTROL REGISTER G

CONTROL REGISTER H

Control Register A

CRA:0 Data/Program Mode. This bit controls the operating mode of the AD73360. If CRA:1 is 0, then a 0 in this bit

places the part in Program Mode. If CRA:1 is 0, then a 1 in this bit places the part in Data Mode.

CRA:1 Mixed Mode. If this bit is a 0, then the operating mode is determined by CRA:0. If this bit is a 1, then the

part operates in Mixed Mode.

CRA:2 Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation.

CRA:3 SPORT Loop Back. This is a diagnostic mode. This bit should be set to 0 to ensure correct operation.

CRA:4–6 Device Count Bits. These bits tell the AD73360 how many devices are used in a cascade. All devices in the

cascade should be programmed to the same value ensure correct operation. See Table XVIII.

CRA:7 Reset. Writing a 1 to this bit will initiate a software reset of the AD73360.

Control Register B

CRB:0–1 Decimation Rate. These bits are used to set the decimation of the AD73360. See Table VII.

CRB:2–3 Serial Clock Divider. These bits are used to set the serial clock frequency. See Table VI.

CRB:4–6 Master Clock Divider. These bits are used to set the Master Clock Divider ratio. See Table V.

CRB:7 Control Echo Enable. Setting this bit to a 1 will cause the AD73360 to write out any control words it receives.

This is used as a diagnostic mode. This bit should be set to 0 for correct operation in Mixed Mode or Data Mode.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

AD73360ARZ

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog Front End - AFE IC 6-CH AFE Processor

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AD73360ARZ

AD73360ARZ

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