CYRS1543AV18
CYRS1545AV18
Document Number: 001-60007 Rev. *L Page 11 of 34
Truth Table
CYRS1543AV18 and CYRS1545AV18
[2, 3, 4, 5, 6, 7]
Operation K RPS WPS DQ DQ DQ DQ
Write cycle:
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
L–H H
[8]
L
[9]
D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
Read cycle: (2.0 Cycle
Latency) Load address
on the rising edge of K;
wait two cycles; read
data on two consecutive
K and K
rising edges.
L–H L
[9]
X Q(A) at K(t + 2) Q(A + 1) at K(t + 2) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 3)
NOP: No operation L–H H H D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
Standby: Clock stopped Stopped X X Previous state Previous state Previous state Previous state
Write Cycle Descriptions
CYRS1543AV18
[2, 10]
BWS
0
BWS
1
K
K
Comments
L L L–H – During the data portion of a write sequence:
CYRS1543AV18 both bytes (D
[17:0]
) are written into the device.
L L – L–H During the data portion of a write sequence
CYRS1543AV18 both bytes (D
[17:0]
) are written into the device.
L H L–H – During the data portion of a write sequence:
CYRS1543AV18 only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
L H – L–H During the data portion of a write sequence
CYRS1543AV18 only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
H L L–H – During the data portion of a write sequence
CYRS1543AV18 only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
H L – L–H During the data portion of a write sequence
CYRS1543AV18 only the upper byte (D
[17:9]
) is written into the device, D
[8:0]
remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K
rising edges. Data outputs are delivered on K and K rising edges.
7. We recommend that K = K
= HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS
0
, BWS
1
, BWS
2
,
and BWS
3
can be altered on different portions
of a write cycle, as long as the setup and hold requirements are achieved.
