CYRS1543AV18
CYRS1545AV18
Document Number: 001-60007 Rev. *L Page 6 of 34
Pin Definitions
Pin Name I/O Pin Description
D
[x:0]
Input-
Synchronous
Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
CYRS1543AV18 D
[17:0]
CYRS1545AV18 D
[35:0]
WPS Input-
Synchronous
Write port select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
Input-
Synchronous
Byte write select (BWS) 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks
when write operations are active. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CYRS1543AV18 BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CYRS1545AV18 BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,
BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27].
All the BWS are sampled on the same edge as the data. Deselecting a BWS ignores the corresponding
byte of data and it is not written into the device
.
A
[x:0]
Input-
Synchronous
Address inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 4 M × 18 (4 arrays each of 1 M × 18) for CYRS1543AV18 and 2 M × 36 (4 arrays each of
512 K × 36) for CYRS1545AV18. Therefore, only 20 address inputs for CYRS1543AV18 and 19 address
inputs for CYRS1545AV18. These inputs are ignored when the appropriate port is deselected.
Q
[x:0]
Outputs-
Synchronous
Data output signals. These pins drive out the requested data when the read operation is active. Valid
data is driven out on the rising edge of the K and K
clocks during read operations. On deselecting the
read port, Q
[x:0]
are automatically tristated.
CYRS1543AV18 Q
[17:0]
CYRS1545AV18 Q
[35:0]
RPS Input-
Synchronous
Read port select Active LOW. Sampled on the rising edge of positive input clock (K). When active,
a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tristated following the next rising edge of
the K clock. Each read access consists of a burst of four sequential transfers.
QVLD Valid Output
Indicator
Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ
.
K Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[x:0]
when in single clock mode.
CQ Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
K. The timings for the echo clocks are shown in the Switching Characteristics on page 25.
CQ
Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
K
. The timings for the echo clocks are shown in the Switching Characteristics on page 25.
ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ
, and Q
[x:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF Input DLL turn off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operation differs from those listed in this data sheet. For normal operation,
this pin can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in
QDR I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up
to 167 MHz with QDR I timing.
TDO Output Test data out (TDO) Pin for JTAG.
