CYRS1543AV18
CYRS1545AV18
Document Number: 001-60007 Rev. *L Page 16 of 34
TAP Controller Block Diagram
0
012..29
3031
Boundary Scan Register
Identification Register
012..
.
.108
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
TAP Electrical Characteristics
Over the Operating Range
Parameter
[14, 15, 16]
Description Test Conditions Min Max Unit
V
OH1
Output HIGH voltage I
OH
=2.0 mA 1.4 V
V
OH2
Output HIGH voltage I
OH
=100 A1.6V
V
OL1
Output LOW voltage I
OL
= 2.0 mA 0.4 V
V
OL2
Output LOW voltage I
OL
= 100 A–0.2V
V
IH
Input HIGH voltage 0.65 × V
DD
V
DD
+ 0.3 V
V
IL
Input LOW voltage –0.3 0.35 × V
DD
V
I
X
Input and output load current GND V
I
V
DD
–5 5 A
Notes
14. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in Electrical Characteristics on page 22.
15. Overshoot: V
IH(AC)
< V
DDQ
+ 0.85 V (Pulse width less than t
CYC
/2), Undershoot: V
IL(AC)
> 1.5 V (Pulse width less than t
CYC
/2).
16. All Voltage referenced to Ground.
CYRS1543AV18
CYRS1545AV18
Document Number: 001-60007 Rev. *L Page 17 of 34
TAP AC Switching Characteristics
Over the Operating Range
Parameter
[17, 18]
Description Min Max Unit
t
TCYC
TCK clock cycle time 50 ns
t
TF
TCK clock frequency 20 MHz
t
TH
TCK clock HIGH 20 ns
t
TL
TCK clock LOW 20 ns
Setup Times
t
TMSS
TMS setup to TCK clock rise 5 ns
t
TDIS
TDI setup to TCK clock rise 5 ns
t
CS
Capture setup to TCK rise 5 ns
Hold Times
t
TMSH
TMS hold after TCK clock rise 5 ns
t
TDIH
TDI hold after clock rise 5 ns
t
CH
Capture hold after clock rise 5 ns
Output Times
t
TDOV
TCK clock LOW to TDO valid 10 ns
t
TDOX
TCK clock LOW to TDO invalid 0 ns
Notes
17. t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
18. Test conditions are specified using the load in TAP AC Test Conditions. t
R
/t
F
= 1 ns.
CYRS1543AV18
CYRS1545AV18
Document Number: 001-60007 Rev. *L Page 18 of 34
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions.
[19]
Figure 3. TAP Timing and Test Conditions
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50
GND
0.9 V
50
1.8 V
0 V
ALL INPUT PULSES
0.9 V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
Note
19. Test conditions are specified using the load in TAP AC Test Conditions. t
R
/t
F
= 1 ns.

5962F1120202QXA

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 72M PARALLEL 165CCGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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