BELASIGNA 250
http://onsemi.com
12
Internal Power Supplies
Power management circuitry in BELASIGNA 250 generates separate digital (VDDC) and analog (VREG, VDBL) regulated
supplies. Each supply requires an external decoupling capacitor, even if the supply is not used externally. Decoupling capacitors
should be placed as close as possible to the power pads. Further details on these critical signals are provided in Table 5.
Non−critical signals are outlined in Table 6.
Table 5. CRITICAL SIGNALS
Pin Name Description Routing Guideline
VBAT Power supply
Place 1 mF (min) decoupling capacitor close to pin. Connect
negative terminal of capacitor to DGND plane.
VREG, VDBL Internal regulator for analog sections
Place separate 1 mF decoupling capacitors close to each pin. Con-
nect negative capacitor terminal to AGND. Keep away from digital
traces and output traces. VREG may be used to generate micro-
phone bias. VDBL shall not be used to supply external circuitry.
AGND Analog ground return Connect to AGND plane.
VDDO / VDDC Internal regulator for digital sections
(pads and core)
Place 10 mF decoupling capacitor close to pin. Connect negative
terminal of capacitor to DGND.
GNDO / GNDC Digital ground return (pads and core) Connect to digital ground.
AI0, AI1 / LOUT,
AI2, AI3
Microphone inputs Keep as short as possible. Keep away from all digital traces and
audio outputs. Avoid routing in parallel with other traces. Connect
unused inputs to AGND.
AIR Input stage reference voltage Connect to AGND. If no analog ground plane, should share trace
with microphone grounds to star point.
AO0, AO1 Analog audio output Keep away from microphone inputs.
RCVR0+, RCVR0−,
RCVR1+, RCVR1−
Direct digital audio output Keep away from analog traces, particularly microphone inputs.
Route corresponding traces as differential pair; route parallel to each
other and approximately the same length.
AOR Output stage reference voltage Connect to star point. Share trace with power amplifier (if present).
RCVRGND Output stage ground return Connect to star point. Keep away from analog inputs.
EXT_CLK External clock input / internal clock
output
Minimize trace length. Keep away from analog signals. If possible,
surround with digital ground.
AI_RC Infrared receiver input If used, minimize trace length to photodiode.
Not available on the CABGA option
Table 6. NON−CRITICAL SIGNALS
Pin Name Description Routing Guideline
CAP0, CAP1 Internal charge pump − capacitor connection Place 100 nF capacitor close to pins
DEBUG_TX, DEBUG_RX Debug port Not critical − Connect to test points
TWSS_SDA, TWSS_CLK TWSS port Not critical
GPIO[14..0] General−purpose I/O Not critical
GPIO[15] General−purpose I/O
Determines voltage mode during boot. For 1.8 V
operation, should be connected to DGND.
Not critical
UART_RX, UART_TX General−purpose UART Not critical
PCM_FRAME, PCM_CLK,
PCM_OUT, PCM_IN
Pulse code modulation port Not critical − Keep away from analog signals.
I2S_INA, I2S_IND, I2S_FA,
I2S_FD, I2S_OUTA, I2S_OUTD
I
2
S compatible port Not critical
UCLK Programmable clock output Not critical −
If used, keep away from analog inputs/outputs
LSAD[5..0] Low−speed A/D converters Not critical
SPI_CLK, SPI_CS,
SPI_SERI, SPI_SERO
Serial peripheral interface port
Connect to EEPROM
Not critical
