0W888-002-XTP Datasheet 0W888-002-XTP, 0W633-001-XTP | P13-P15

BELASIGNA 250

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Audio Inputs

The audio input traces should be as short as possible. The

input impedance of each audio input pad (e.g., AI0, AI1,

etc.,) is high (approximately 500 kW); therefore a 10 nF

capacitor is sufficient to decouple the DC bias. This

capacitor and the internal resistance form a first−order

analog high pass filter whose cutoff frequency can be

calculated by f

3dB

(Hz) = 1/(R x C x 2π), which results with

~30 Hz for 10 nF capacitor. This 10 nF capacitor value

applies when the preamplifier is being used, in other words,

when a non−unity gain is applied to the signals. When the

preamplifier is by−passed, the impedance is reduced; hence,

the cut−off frequency of the resulting high−pass filter could

be too high. In such a case, the use of a 30−40 nF serial

capacitor is recommended.

Keep audio input traces strictly away from output traces.

Microphone ground terminals should be connected to the

AGND plane (if present) or share a trace with the input

ground reference voltage pin (AIR) to the star point. Analog

and digital outputs MUST be kept away from microphone

inputs to ensure low noise performance.

Audio Outputs

The audio output traces should be as short as possible. If

the direct digital output is used, the trace length of RCVRx+

and RCVRx− should be approximately the same to provide

matched impedances. If the analog audio output is used, the

ground return for the external power amplifier should share

a trace with the output ground reference voltage pin (AOR)

to the star point.

Architecture Overview

Figure 2. BELASIGNA 250 Architecture: A Complete Audio Processing System

RCore DSP

The RCore is a 16−bit fixed−point, dual−Harvard

architecture DSP. It includes efficient normalize and

de−normalize instructions, and support for double precision

operations to provide the additional dynamic range needed

for many applications. All memory locations in the system

are accessible by the RCore using several addressing modes

including indirect and circular modes. The RCore assumes

master functionality of the system.

RCore DSP Architecture

Figure 3 illustrates the architecture of the RCore.

BELASIGNA 250

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Figure 3. RCore DSP Architecture

XRAM

X_Bus

YRAM

Y_Bus

Y_AGU

Data registers

Address and Control registers

P_Bus

PCFG6

PCFG5

PCFG4

CTRL

Multiplier

PH PL

ALU

Barrel

Shifter

DCU

AE AH AL

Limiter

EXP

Internal Routing

Immediate

PRAM

PCU

LC0 LC1 REP

D_SYS_CTRL

D_INT_EBL

D_INT_STATUS

EXT3

D_AUX_REG4

D_AUX_REG0

X_AGU

PCFG2

PCFG1

PCFG0

The RCore is a single−cycle pipelined multiply−

accumulate (MAC) architecture that feeds into a 40−bit

accumulator complete with barrel shifter for fast

normalization and de−normalization operations. Program

execution is controlled by a sequencer that employs a

three−stage pipeline (FETCH, DECODE, EXECUTE).

Furthermore, the RCore incorporates pointer configuration

registers for low cycle−count address generation when

accessing the three memories: program memory (PRAM),

X data memory (XRAM) and Y data memory (YRAM).

Instruction Set

The RCore instruction set can be divided into the

following three classes:

1. Arithmetic and Logic Instructions

The RCore uses two’s−complement fractional as a native

data format. Thus, the range of valid numbers is [−1; 1),

which is represented by 0x8000 to 0x7FFF. Other formats

can be utilized by applying appropriate shifts to the data.

The multiplier takes 16−bit values and performs a

multiplication every time an operand is loaded into either the

X or Y registers. A number of instructions that allow loading

of X and Y simultaneously and addition of the new product

to the previous product (a MAC operation) are available.

Single−cycle MAC with data pointer update and fetch is

supported.

The arithmetic logic unit (ALU) receives its input from

either the accumulator (AE|AH|AL) or the product register

(PH|PL). Although the RCore is a 16−bit system, 32−bit

additions or subtractions are also supported. Bit

manipulation is also available on the accumulator, as are

operations to perform arithmetic or logic shifting, toggling

of specific bits, limiting, and other functions.

2. Data Movement Instructions

Data movement instructions transfer data between RAM,

control registers and the RCore’s internal registers

(accumulator, PH, PL, etc.).

Two address generators are available to simultaneously

generate two addresses in a single cycle. The address

pointers R0..2 and R4..6 can be configured to support

increment, decrement, add−by−offset, and two types of

modulo−N circular buffer operations. Single−cycle access

to low−X memory or low−Y memory as well as two−cycle

instructions for immediate access to any address, are also

available.

3. Program Flow Control Instructions

The RCore supports repeating of both single−word

instructions and larger segments of code using dedicated

repeat instructions or hardware loop counters. Furthermore,

instructions to manipulate the program counter (PC) register

such as calls to subroutines, conditional branches and

unconditional branches are also provided.

The full instruction set may be seen in Table 7.

BELASIGNA 250

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Table 7. INSTRUCTION SET

Instruction

Description

ABS A [,Cond] [,DW] Calculate absolute value of A

on condition

ADD A, Reg [,C] Add register to A

ADD A, (Rij) [,C] Add memory to A

ADD A, DRAM [,B] Add (DRAM) to A

ADD A, (Rij)p [,C] Add program memory to A

ADD A, Rc [,C] Add Rc register to A

ADDI A, IMM [,C] Add IMM to A

ADSI A, SIMM Add signed SIMM to A

AND A, Reg AND register with AH to AH

AND A, (Rij) AND memory with AH to AH

AND A, DRAM [,B] AND (DRAM) with AH to AH

AND A, (Rij)p AND program memory with AH to AH

AND A, Rc AND Rc register with AH to AH

ANDI A, IMM AND IMM with AH to AH

ANSI A, SIMM AND unsigned SIMM with AH to AH

BRA PRAM [,Cond] Branch to new address on condition

BREAK Stop the DSP for debugging purposes

CALL PRAM [,Cond] [,B] Push PC and branch to new address

on condition

CLB A Calculate the leading bits on A

CLR A [,DW] Clear accumulator

CLR Reg Clear register

CMP A, Reg [,C] Compare register to A

CMP A, (Rij) [,C] Compare memory to A

CMP A, DRAM [,B] Compare (DRAM) to A

CMP A, (Rij)p [,C] Compare program memory to A

CMP A, Rc [,C] Compare Rc register to A

CMPI A, IMM [,C] Compare IMM to A

CMSI A, SIMM Compare signed SIMM to A

CMPL A [,Cond] [,DW] Calculate logical inverse of A

on condition

DADD [Cond] [,P] Add PH | PL to A, update PH | PL on

condition

DBNZ0/1 PRAM Branch to new address if LC0/1 <> 0

DCMP Compare PH | PL to A

DEC A [,Cond] [,DW] Decrement A on condition

DEC Reg [Cond] Decrement register on condition

DEC (Rij) [,Cond] Decrement memory on condition

DSUB [Cond] [,P] Subtract PH | PL from A, update

PH | PL on condition

EOR A, Reg Exclusive−OR register with AH to AH

EOR A, (Rij) Exclusive−OR memory with AH to AH

Instruction Description

EOR A, DRAM [,B] Exclusive−OR (DRAM) with AH to AH

EOR A, (Rij)p Exclusive−OR program memory with

AH to AH

EOR A, Rc Exclusive−OR Rc register with

AH to AH

EORI A, IMM Exclusive−OR IMM with AH to AH

EOSI A, SIMM Exclusive−OR unsigned SIMM with

AH to AH

INC A [,Cond] [,DW] Increment A on condition

INC Reg [,Cond] Increment register on condition

INC (Rij) [,Cond] Increment memory on condition

LD Rc, Rc Load Rc register with Rc register

LD Reg, Reg Load register with register

LD Reg, (Rij) Load register with memory

LD (Rij), Reg Load memory with register

LD (Ri), (Rj) Transfer Y mem data to X mem

LD (Rj), (Ri) Transfer X mem data to Y mem

LD A, DRAM [,B] Load A with (DRAM)

LD DRAM, A [,B] Load (DRAM) with A

LD Rc, (Rij) Load Rc register with memory

LD (Rij), Rc Load memory with Rc register

LD Reg, (Rij)p Load register with program memory

LD (Rij)p, Reg Load program memory with register

LD Reg, (Reg)p Load register with program memory

via register

LD Reg, Rc Load register with Rc register

LD Rc, Reg Load Rc register with register

LDI Reg, IMM Load register with IMM

LDI Rc, IMM Load Rc register with IMM

LDI (Rij), IMM Load memory with IMM

LDSI LC0/1 SIMM Load loop counter with 16−bit unsigned

SIMM

LDSI A, SIMM Load A with signed SIMM

LDSI Rij, SIMM Load pointer register with unsigned

SIMM

MLD (Rj), (Ri) [,SQ] Multiplier load and clear A

MLD Reg, (Ri) [,SQ] Multiplier load and clear A

MODR Rj, Ri Pointer register modification

MPYA (Rj), (Ri) [,SQ] Multiplier load and accumulate

MPYA Reg, (Ri) [,SQ] Multiplier load and accumulate

MPYS (Rj), (Ri) [,SQ] Multiplier load and accumulate

negative

MPYS Reg, (Ri) [,SQ] Multiplier load and accumulate

negative

MSET (Rj), (Ri) [,SQ] Multiplier load

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0W888-002-XTP

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Digital Signal Processors & Controllers - DSP, DSC BELASIGNA 250 LFBGA 7X7

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