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0W888-002-XTP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
BELASIGNA 250
http://onsemi.com
4
Table 2. ELECTRICAL SPECIFICATIONS (continued)
Description ScreenedUnitsMaxTypMinConditionsSymbol
POWER−ON−RESET (POR)
POR hysteresis
POR
HYSTERESIS
10 16 22 mV
POR duration T
POR
5 10 15 ms
INPUT STAGE
Analog input voltage
V
IN
0 − 2 V
Preamplifier gain tolerance PAG 1 kHz −1.5 − 1.5 dB √
Preamplifier gain mismatch be-
tween channels
1 kHz −1 − 1 dB
Input impedance R
IN
0 dB preamplifer gain − 250 −
kW
Non−zero preamplifier gains 400 550 700
kW
√
Input referred noise IN
IRN
Unweighted,
20 Hz to 8 kHz BW
Preamplifier setting:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
−
−
−
−
−
−
−
−
40
12
8
6
4.5
4
3.5
3
55
14
11
8
5.5
5
4.5
4
mVrms
Input dynamic range IN
DR
1 kHz, 20 Hz to 8 kHz BW
Preamplifier setting:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
85
84
84
83
82
81
80
78
88
87
87
86
85
84
83
81
−
−
−
−
−
−
−
−
dB
Input peak THD+N (Note 4) IN
THDN
Any valid preamplifier gain,
1 kHz
− −63 −60 dB √
Input stage delay (Note 5) − 200 −
ms
DIRECT DIGITAL OUTPUT
Maximum load current
I
DO
Normal mode − − 13 mA
High power mode − − 25 mA
Output impedance R
DO
Normal mode − 9 11
W
High power mode − 5 6
W
Output dynamic range DO
DR
Unweighted, 100 Hz to
8 kHz BW, mono
90 93 − dB
Output THD+N DO
THDN
Unweighted, 100 Hz to
22 kHz BW, mono
−79 −76 dB
Output voltage DO
VOUT
−Vbat Vbat V
ANALOG OUTPUT STAGE
Analog output voltage
V
OUT
0 − 2 V
3. Audio performance will be degraded below 1.05 V.
4. Measured with a = 12 dB input signal.
5. Input stage delay is inversely proportional to sampling frequency.
6. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
BELASIGNA 250
http://onsemi.com
5
Table 2. ELECTRICAL SPECIFICATIONS (continued)
Description ScreenedUnitsMaxTypMinConditionsSymbol
ANALOG OUTPUT STAGE
Attenuator gain tolerance
ATG Input is –6 dB re: full scale @
1 kHz (all preamplifier gains)
−1 − 1 dB √
Output impedance R
OUT
Attenuator settings:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
1
9
7
4
3
2
1
1
2
13
10
8
6
4
3
2
5
17
14
12
9
7
6
5
kW
√
Output noise OUT
N
0 dB attenuation − 33 40
mV
Output dynamic range OUT
DR
Unweighted, 100 Hz to
8 kHz BW, mono
85 87 − dB
Output THD+N OUT
THDN
Unweighted, 100 Hz to
22 kHz BW, mono
− −70 −67 dB
ANTI−ALIASING FILTERS (Input and Output)
Preamplifier filter cut−off frequency
Preamp not bypassed − 25 − kHz
Digital anti−aliasing filter cut−off
frequency
− f
s
/2 −
Analog output cut−off frequency
25 kHz 15 25 35 kHz
12 kHz (only output filter) 9 12 15 kHz
Passband flatness −1 − 1 dB
Stopband attenuation 60 kHz (12 kHz cut−off) − 60 − dB
LOW−SPEED A/D
Input voltage
Peak input voltage 0 − 2.0 V √
INL From GND to 2*VREG − − 10 LSB
DNL From GND to 2*VREG − − 2 LSB
Maximum variation over
temperature (0_C to 50_C)
− − 5 LSB
Sampling frequency All channels sequentially − 12.8 − kHz
Channel sampling frequency 8 channels − 1.6 − kHz
DIGITAL PADS
Voltage level for high input
V
IH
VDDC
* 0.8
− VDDC
+ 0.5
(Note 6)
V
Voltage level for low input V
IL
−0.3 − VDDC
* 0.2
V
Input capacitance for digital pads C
IN
− 2 − pF
Pull−up resistance for digital input
pads
R
UP_IN
− 260 −
kW
√
Pull−down resistance to VDDC fo
r
digital input pads
R
DOWN_IN
VDDC = 1.0 V − 430 −
kW
VDDC = 1.25 V − 260 −
kW
√
VDDC = 2.0 V − 140 −
kW
3. Audio performance will be degraded below 1.05 V.
4. Measured with a = 12 dB input signal.
5. Input stage delay is inversely proportional to sampling frequency.
6. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
BELASIGNA 250
http://onsemi.com
6
Table 2. ELECTRICAL SPECIFICATIONS (continued)
Description ScreenedUnitsMaxTypMinConditionsSymbol
DIGITAL PADS
Pull−up resistance for digital input
pads
R
UP_IN
− 260 −
kW
√
Rise and fall time Tr, Tf Digital output pad − − 100 ns
ESD Human Body Model 2 − − kV
Latch−up V < GNDO, V > VDDO 200 − − mA
OSCILLATION CIRCUITRY
Internal oscillator frequency
SYS_CLK 0.5 − 10.24 MHz
Calibrated clock frequency SYS_CLK −1 ±0 +1 % √
Internal oscillator jitter System clock: 1.28 MHz − 0.4 1 ns
External oscillator tolerances
Duty cycle 45 50 55 %
System clock: 50 MHz − − 300 ps
Maximum working frequency CLK
MAX
External clock; VBAT: 1.25 V − − 10 MHz
External clock; VBAT: 1.8 V − − 50 MHz
IR INTERFACE
Carrier frequency
39 40 41 kHz
Data rate 1150 1200 1250 bit/s
Input current 0.1 − 15
mA
DIGITAL INTERFACES
TWSS baud rate
PCLK ≤ 1.92 MHz − − 100 kbps
PCLK > 1.92 MHz − − 400 kbps
General−purpose UART
baud rate
PCLK = 3.81 MHz − − 762 kbps
PCLK = 7.62 MHz − − 1.524 Mbps
Debug port baud rate − − 115.2 kbps
3. Audio performance will be degraded below 1.05 V.
4. Measured with a = 12 dB input signal.
5. Input stage delay is inversely proportional to sampling frequency.
6. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

0W888-002-XTP

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Manufacturer:
ON Semiconductor
Description:
Digital Signal Processors & Controllers - DSP, DSC BELASIGNA 250 LFBGA 7X7
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