BELASIGNA 250
http://onsemi.com
17
Weighted Overlap−Add (WOLA) Filterbank Coprocessor
Figure 4. WOLA Filterbank Coprocessor Architecture
Time−domain
output
3. Filterbank
Synthesis
(Length: Ls = La/DF)
2. Gain
Application
(Real or Complex)
1. Filterbank
Analysis
(Length: La)
Time−domain
input
R
R
R
N/2 bands
(0 to Nyquist)
R
R
R
Band
Processing
Band
Processing
Band
Processing
Down
Sampling
Up
Sampling
The WOLA coprocessor performs low−delay,
high−fidelity filterbank processing to provide efficient
time−frequency processing and alias−free gain adjustments.
The WOLA coprocessor stores intermediate data values as
well as program code and window coefficients in its own
memory space. Audio data are accessed directly from the
input and output FIFOs where they are automatically
managed by the IOP.
The WOLA coprocessor can be configured to provide
different sizes and types of transforms, such as mono, simple
stereo or full stereo configurations. The number of bands,
the stacking mode (even or odd), the oversampling factor
and the shape of the analysis and synthesis windows used are
all configurable. The selected set of parameters affects both
the frequency resolution, the group delay through the
WOLA coprocessor and the number of cycles needed for
complete execution.
The WOLA coprocessor can generate both real and
complex data or energy values that represent the energy in
each band. Either real or complex gains can be applied to the
data. Complex gains provide means for phase adjustments,
which is useful in sub−band directional hearing aid
applications. The RCore always has access to these values
through shared memories. All parameters are configurable
with microcode, which is used to control the WOLA
coprocessor during execution.
The RCore initiates all WOLA functions (analysis, gain
application, synthesis) through dedicated control registers.
A dedicated interrupt is used to signal completion of a
WOLA function.
A large number of standard WOLA microcode
configurations are delivered with the BELASIGNA 250
Evaluation and Development Kit (EDK). These
configurations have been specially designed for low group
delay and high fidelity.
Input/Output Processor (IOP)
The IOP is an audio−optimized configurable DMA unit
for audio data samples. It manages the collection of data
from the A/D converters to the input FIFO and feeds digital
data to the audio output stage from the output FIFO.
The IOP places and retrieves FIFO data in memories
shared with the RCore. Each FIFO (input and output) has
two memory interfaces. The first corresponds with the
normal FIFO. Here the address of the most recent input
block changes as new blocks of samples arrive. The second
corresponds with the Smart FIFO. In this scheme the address
of the most recent input block is fixed. The Smart FIFO
interface is especially useful for time−domain filters.
In the case where the WOLA coprocessor and the IOP no
longer work together as a result of a low battery condition,
an IOP end−of−battery−life auto−mute feature is available.
The IOP can be configured to access data in the FIFOs in
four different audio modes that are shown in Figure 8.
• Mono mode: Input samples are stored sequentially in
the input FIFO. Output samples are stored sequentially
in the output FIFO.
• Simple stereo mode: Input samples from the two
channels are interleaved in the input FIFO. Output
samples for the single output channel are stored in the
lower part of the output FIFO.
• Digital mixed mode: Input samples from the two
channels are stored in each half of the input FIFO.
Output samples for the single output channel are stored
in the lower half of the output FIFO.
• Full stereo mode: Input samples from the two channels
are interleaved in the input FIFO. Output samples for
the two output channels are also interleaved in the
output FIFO.
