BELASIGNA 250
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Mechanical Information and Circuit Design Guidelines
Mechanical Information
BELASIGNA 250 is available in two packages in
production quantities:
A 7 x 7 mm LFBGA package where all the device I/Os
are available at the BGA level
A 5 x 5 mm CABGA package
BELASIGNA 250 also exists in a PLCC package, but it
is only used on the evaluation and development board. The
PLCC package is not available in production quantities. A
separate data sheet is available for this part (part number
0W548−001−XTD). Contact ON Semiconductor for more
information on this package option.
All BELASIGNA 250 package options are Green
(RoHS− compliant). Contact ON Semiconductor for
supporting documentation.
A total of 51 active pins are present on the BELASIGNA 250 7 x 7 mm LFBGA package option. This package contains a
total of 64 balls, organized in an 8−by−8 array. A description of these pins is given in Table 3.
Table 3. LFBGA PIN DESCRIPTIONS
Pad Index BELASIGNA 250 Pin Name Description I/O A/D
F2 VBAT Power supply I A
B3, E2 AGND Analog ground N/A A
E4 RCVRBAT Digital output power supply I A
H4 RCVRGND Digital output ground N/A A
D6 VDDC Digital core power supply O D
F7 GNDC Digital core ground N/A D
H6, C5 VDDO Digital pads power supply I D
A6, F6 GNDO Digital pads ground N/A D
E1 VREG Microphone power supply O A
A1 VDBL Doubled voltage output O A
B2 CAP0 Charge pump capacitor connection N/A A
A2 CAP1 Charge pump capacitor connection N/A A
B1 AI0 Microphone input I A
C1 AI1/LOUT Microphone input / direct audio input I A
C2 AI2 Microphone input I A
D1 AI3 Microphone input I A
F1 AI_RC Remote control input I A
D3 AIR Audio input reference N/A A
G3 RCVR0+ Digital output 0 positive output O A
H3 RCVR0− Digital output 0 negative output O A
H2 AO0/RCVR1+ Analog output 0 / digital output 1 positive output O A
H1 AO1/RCVR1− Analog output 1 / digital output 1 negative output O A
F3 AOR Analog output reference N/A A
H8 DEBUG_RX RS−232 serial input I D
G8 DEBUG_TX RS−232 serial output O D
H7 EXT_CLK External clock input / output I/O D
C3 SPI_CLK SPI clock O D
A3 SPI_CS SPI chip select O D
B4 SPI_SERO SPI serial output O D
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Table 3. LFBGA PIN DESCRIPTIONS (continued)
Pad Index A/DI/ODescriptionBELASIGNA 250 Pin Name
A4 SPI_SERI SPI serial input I D
E6 TWSS_CLK Two−wire synchronous serial clock I/O D
F8 TWSS_DATA Two−wire synchronous serial data I/O D
G5 GPIO[0] / I2S_FD General−purpose input or output / I2S digital frame I/O D
H5 GPIO[1] / I2S_IND General−purpose input or output / I2S digital input I/O D
G4 GPIO[2] / I2S_INA General−purpose input or output / I2S analog input I/O D
F5 GPIO[3] / NCLK_DIV_RESET / I2S_FA General−purpose input or output / I2S analog frame I/O D
B5 GPIO[4] / LSAD [0] / I2S_OUTD General−purpose input or output / low−speed A/D input /
I2S digital output
I/O D/A
A5 GPIO[5] / LSAD[1] / I2S_OUTA General−purpose input or output / low−speed A/D input /
I2S analog output
I/O D/A
B6 GPIO[6] / LSAD[2] General−purpose input or output / low−speed A/D input I/O D/A
A7 GPIO[7] / LSAD[3] General−purpose input or output / low−speed A/D input I/O D/A
A8 GPIO[8] / LSAD[4] / UART_TX General−purpose input or output / low−speed A/D input /
UART output
I/O D/A
B7 GPIO[9] / LSAD[5] / UART_RX General−purpose input or output / low−speed A/D input /
UART input
I/O D/A
B8 GPIO[10] / UCLK General−purpose input or output / user clock I/O D
C7 GPIO[11] / PCM_CLK General−purpose input or output / PCM clock I/O D
C8 GPIO[12] / PCM_SERI General−purpose input or output / PCM serial input I/O D
D7 GPIO[13] / PCM_SERO General−purpose input or output / PCM serial output I/O D
D8 GPIO[14] / PCM_FRAME General−purpose input or output / PCM frame I/O D
E7 GPIO[15] General−purpose input or output I/O D
NOTE: Unlisted pads must be left unconnected.
Weight
BELASIGNA 250 LFBGA (0W888−002−XTP) has an average weight of 0.1275 grams.
A total of 49 active pins are present on this CABGA package of BELASIGNA 250. A description of these pads is given in
Table 4.
Table 4. CABGA PIN DESCRIPTIONS
Pad Index
BELASIGNA 250 Pad Name Description I/O A/D
H7 VBAT Power supply I A
H5, J6, H6 AGND Analog ground N/A A
H8 RCVRBAT Digital output power supply I A
G8 RCVRGND Digital output ground N/A A
D9, C3 VDDC Digital core power supply O D
C8 GNDC Digital core ground N/A D
J5 VREG Regulated microphone power supply O A
J1 VDBL Doubled voltage output O A
F1 SPI_CS SPI chip select O D
G2 SPI_CLK SPI Clock O D
F2 SPI_SERO SPI serial output O D
E1 SPI_SERI SPI serial input I D
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Table 4. CABGA PIN DESCRIPTIONS (continued)
Pad Index A/DI/ODescriptionBELASIGNA 250 Pad Name
H1 CAP0 Charge pump capacitor connection N/A A
G1 CAP1 Charge pump capacitor connection N/A A
J2 AI0 Microphone input I A
H3 AI1/LOUT Microphone input / line−out audio output I/O A
J4 AI2 Microphone input I A
H4 AI3 Microphone input I A
J3 AIR Audio input reference N/A A
G9 RCVR0+ Digital output 0 positive output O A
H9 RCVR0− Digital output 0 negative output O A
J9 AO0/RCVR1+ Analog output 0 / digital output 1 positive output O A
J8 AO1/RCVR1− Analog output 1 / digital output 1 negative output O A
J7 AOR Analog output reference N/A A
B9 DEBUG_RX RS−232 serial input I D
A9 DEBUG_TX RS−232 serial output O D
C9 EXT_CLK External clock input / internal clock output I/O D
A7 TWSS_CLK Two−wire synchronous serial clock I/O D
A8 TWSS_DATA Two−wire synchronous serial data I/O D
E8 GPIO[0] / I2S_FD General−purpose input or output / I2S digital frame I/O D
E9 GPIO[1] / I2S_IND General−purpose input or output / I2S digital input I/O D
F8 GPIO[2] / I2S_INA General−purpose input or output / I2S analog input I/O D
F9 GPIO[3] / NCLK_DIV_RESET / I2S_FA General−purpose input or output / I2S analog frame I/O D
D2 GPIO[4] / LSAD [0] / I2S_OUTD General−purpose input or output / low−speed A/D input /
I2S digital output
I/O A/D
D1 GPIO[5] / LSAD[1] / I2S_OUTA General−purpose input or output / low−speed A/D input /
I2S analog output
I/O A/D
C1 GPIO[6] / LSAD[2] General−purpose input or output / low−speed A/D input I/O A/D
B1 GPIO[7] / LSAD[3] General−purpose input or output / low−speed A/D input I/O A/D
A1 GPIO[8] / LSAD[4] / UART_TX General−purpose input or output / low−speed A/D input /
UART output
I/O A/D
A2 GPIO[9] / LSAD[5] / UART_RX General−purpose input or output / low−speed A/D input /
UART input
I/O A/D
A3 GPIO[10] / UCLK General−purpose input or output / user clock I/O D
B4 GPIO[11] / PCM_CLK General−purpose input or output / PCM clock I/O D
A4 GPIO[12] / PCM_SERI General−purpose input or output / PCM serial input I/O D
B5 GPIO[13] / PCM_SERO General−purpose input or output / PCM serial output I/O D
A5 GPIO[14] / PCM_FRAME General−purpose input or output / PCM frame I/O D
A6 GPIO[15] General−purpose input or output I/O D
NOTE: There are 9 unlisted pads that must be left unconnected. (B2, B3, B6, B7, B8, C2, D8, E2, H2)

0W888-002-XTP

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Signal Processors & Controllers - DSP, DSC BELASIGNA 250 LFBGA 7X7
Lifecycle:
New from this manufacturer.
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