AD7890BRZ-4REEL Datasheet AD7890ARZ-10, AD7890ANZ-4, AD7890BRZ-2 | P10-P12

AD7890

Rev. C | Page 9 of 28

TERMINOLOGY

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f

/2), excluding dc.

The ratio is dependent upon the number of quantization levels

in the digitization process; the more levels, the smaller the

quantization noise. The theoretical signal to (noise + distortion)

ratio for an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7890, it is defined as

log20)dB(

VVVVV

THD

++++

where:

is the rms amplitude of the fundamental and

, V

and V

are the rms amplitudes of the second

through the sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

parts where the harmonics are buried in the noise floor, it is

determined by a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities creates distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for

which neither m nor n are equal to zero. For example, the

second-order terms include (fa + fb) and (fa − fb), while the

third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and

(fa − 2fb).

The AD7890 is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second and third order terms are of different

significance. The second-order terms are usually distanced in

frequency from the original sine waves while the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

as per the THD specification where it is the ratio of the rms

sum of the individual distortion products to the rms amplitude

of the fundamental expressed in dBs.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk

between channels. It is measured by applying a full-scale 1 kHz

signal to any one of the other seven inputs and determining how

much that signal is attenuated in the channel of interest. The figure

given is the worst case across all eight channels.

Relative Accuracy

Relative accuracy or endpoint nonlinearity is the maximum

deviation from a straight line passing through the endpoints of

the ADC transfer function.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Positive Full-Scale Error (AD7890-10)

This is the deviation of the last code transition (01 . . . 110 to

01 . . . 111) from the ideal (4 × REF IN − 1 LSB) after the

bipolar zero error has been adjusted out.

Positive Full-Scale Error (AD7890-4)

This is the deviation of the last code transition (11 . . . 110 to

11 . . . 111) from the ideal (1.638 × REF IN − 1 LSB) after the

unipolar offset error has been adjusted out.

Positive Full-Scale Error (AD7890-2)

This is the deviation of the last code transition (11 . . . 110 to

11 . . . 111) from the ideal (REF IN − 1 LSB) after the unipolar

offset error has been adjusted out.

Bipolar Zero Error (AD7890-10)

This is the deviation of the midscale transition (all 0s to all 1s)

from the ideal 0 V (AGND).

Unipolar Offset Error (AD7890-2, AD7890-4)

This is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal 0 V (AGND).

Negative Full-Scale Error (AD7890-10)

This is the deviation of the first code transition (10 . . . 000 to

10 . . . 001) from the ideal (−4 × REF IN + 1 LSB) after bipolar

zero error has been adjusted out.

Track/Hold Acquisition Time

Track/hold acquisition time is the time required for the output

of the track/hold amplifier to reach its final value, within

±1/2 LSB, after the end of conversion (the point at which the

track/hold returns to track mode). It also applies to situations

where a change in the selected input channel takes place or

where there is a step input change on the input voltage applied

to the selected V

input of the AD7890. It means that the user

must wait for the duration of the track/hold acquisition time

after the end of conversion or after a channel change/step input

change to V

before starting another conversion, to ensure that

the part operates to specification.

AD7890

Rev. C | Page 10 of 28

CONTROL REGISTER

The control register for the AD7890 contains 5 bits of information.

Six serial clock pulses must be provided to the part in order to

write data to the control register (seven if the write is required

to put the part in standby mode). If

TFS

returns high before six

serial clock cycles, then no data transfer takes place to the

control register and the write cycle has to be restarted to write

the data to the control register.

If, however, the CONV bit of the register is set to a Logic 1, then

a conversion is initiated whenever a control register write takes

place regardless of how many serial clock cycles the

TFS

remains low for. The default (power-on) condition of all bits in

the control register is 0.

MSB LSB

A2 A1 A0 CONV STBY

Table 3.

Bit Name Description

A2 Address Input. This input is the most significant address input for multiplexer channel selection.

A1 Address Input. This is the 2nd most significant address input for multiplexer channel selection.

Address Input. Least significant address input for multiplexer channel selection. When the address is written to the control

EXT

pin. When

this pulse is active, it ensures the conversion process cannot be activated. This allows for the multiplexer settling time,

track/hold acquisition time before the track/hold goes into hold, and the conversion is initiated. In applications where there is

an antialiasing filter between the MUX OUT pin and the SHA IN pin , the filter settling time can be taken into account before the

input on the SHA IN pin is sampled. When the internal pulse times out, the track/hold goes into hold and conversion is initiated.

CONV

Conversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to the

CONVST input. Continuous conversion

starts do not take place when there is a 1 in this location. The internal pulse and the conversion process are initiated after the

sixth serial clock cycle of the write operation if a 1 is written to this bit. With a 1 in this bit, the hardware conversion start (the

CONVST input) is disabled. Writing a 0 to this bit enables the hardware CONVST input.

STBY

Standby Mode Input. Writing a 1 to this bit places the device in its standby, or power-down, mode. Writing a 0 to this bit places

the device in its normal operating mode. The part does not enter its standby mode until the seventh falling edge of SCLK in a

write operation. Therefore, the part requires seven serial clock pulses in its serial write operation if it is required to put the part

into standby.

AD7890

Rev. C | Page 11 of 28

THEORY OF OPERATION

CONVERTER DETAILS

The AD7890 is an 8-channel, 12-bit, single supply, serial data

acquisition system. It provides the user with signal scaling,

multiplexer, track/hold, reference, ADC, and versatile serial

logic functions on a single chip. The signal scaling allows the

part to handle ±10 V input signals (AD7890-10) and 0 V to

4.096 V input signals (AD7890-4) while operating from a single

5 V supply. The AD7890-2 contains no signal scaling and

accepts an analog input range of 0 V to 2.5 V. The part operates

from a 2.5 V reference, which can be provided from the part’s

own internal reference or from an external reference source.

Unlike other single chip data acquisition solutions, the AD7890

provides the user with separate access to the multiplexer and

the ADC. This means that the flexibility of separate multiplexer

and ADC solutions is not sacrificed with the one-chip solution.

With access to the multiplexer output, the user can implement

external signal conditioning between the multiplexer and the

track/hold. It means that one antialiasing filter can be used on

the output of the multiplexer to provide the antialiasing

function for all eight channels.

Conversion is initiated on the AD7890 either by pulsing the

CONVST

input or by writing a Logic 1 to the CONV bit of the

control register. When using the hardware

CONVST

input, on

the rising edge of the

CONVST

signal, the on-chip track/hold

goes from track to hold mode and the conversion sequence is

started, provided the internal pulse has timed out. This internal

pulse (which appears at the C

EXT

pin) is initiated whenever the

multiplexer address is loaded to the AD7890 control register.

This pulse goes from high to low when a serial write to the part

is initiated. It starts to discharge on the sixth falling clock edge

of SCLK in a serial write operation to the part. The track/hold

cannot go into hold and conversion cannot be initiated until the

EXT

pin has crossed its trigger point of 2.5 V. The discharge

time of the voltage on C

EXT

depends upon the value of capacitor

connected to the C

EXT

pin (see the C

EXT

Functioning section).

The fact that the pulse is initiated every time a write to the

control register takes place means that the software conversion

start and track/hold signal is always delayed by the internal pulse.

The conversion clock for the part is generated from the clock

signal applied to the CLK IN pin of the part. Conversion time

for the AD7890 is 5.9 μs from the rising edge of the hardware

CONVST

signal and the track/hold acquisition time is 2 μs. To

obtain optimum performance from the part, the data read

operation or control register write operation should not occur

during the conversion or during 500 ns prior to the next

conversion.

This allows the part to operate at throughput rates up to

117 kHz in the external clocking mode and achieve data sheet

specifications. The part can operate at slightly higher

throughput rates (up to 127 kHz), again in external clocking

mode with degraded performance (see the Timing and Control

section). The throughput rate for self-clocking mode is limited

by the serial clock rate to 78 kHz.

All unused inputs should be connected to a voltage within the

nominal analog input range to avoid noise pickup. On the

AD7890-10, if any one of the input channels which are not

being converted goes more negative than −12 V, it can interfere

with the conversion on the selected channel.

CIRCUIT DESCRIPTION

The AD7890 is offered as three part types: the AD7890-10

handles a ±10 V input voltage range, the AD7890-4 handles a

0 V to 4.096 V input range, while the AD7890-2 handles a 0 V

to 2.5 V input voltage range.

AD7890-10 Analog Input

Figure 4 shows the analog input section for the AD7890-10. The

analog input range for each of the analog inputs is ±10 V into

an input resistance of typically 33 kΩ. This input is benign with

no dynamic charging currents with the resistor attenuator stage

followed by the multiplexer and, in cases where MUX OUT is

connected to SHA IN, this is followed by the high input

impedance stage of the track/hold amplifier. The designed code

transitions occur on successive integer LSB values (such as:

1 LSB, 2 LSBs, 3 LSBs...). Output coding is twos complement

binary with 1 LSB − FSR/4096 = 20 V/4096 = 4.88 mV. The

ideal input/output transfer function is shown in Table 4.

2.5V

REFERENCE

30kΩ

2kΩ

7.5kΩ

200Ω

10kΩ

AD7890-10

REF OUT/

REF IN

AGND

INX

EQUIVALENT ON-RESISTANCE OF MULTIPLEXER

MUX OUT

TO ADC

REFERENCE

CIRCUITRY

01357-004

Figure 4. AD7890-10 Analog Input Structure

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD7890BRZ-4REEL

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Analog to Digital Converters - ADC LC2MOS 8CH 12B Data Acquisition System

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AD7890BRZ-4REEL

AD7890BRZ-4REEL

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