AD7890
Rev. C | Page 5 of 28
TIMING SPECIFICATIONS
V
DD
= 5 V ± 5%, AGND = DGND = 0 V, REF IN = 2.5 V, f
CLK IN
= 2.5 MHz external, MUX OUT connected to SHA IN.
Parameter
1,
2
Limit at T
MIN
, T
MAX
(A, B, S Versions) Unit Conditions/Comments
f
CLKIN
3
100 kHz min Master Clock Frequency. For specified performance.
2.5 MHz max
t
CLKIN IN LO
0.3 × t
CLK IN
ns min Master Clock Input Low Time.
t
CLK IN HI
0 3 × t
CLK IN
ns min Master Clock Input High Time.
tr
4
25 ns max Digital Output Rise Time. Typically 10 ns.
tf
4
25 ns max Digital Output Fall Time. Typically 10 ns.
t
CONVERT
5.9 μs max Conversion Time.
t
CST
100 ns min
CONVST
Pulse Width.
Self-Clocking Mode
t
1
t
CLK IN HI
+ 50 ns max
RFS
Low to SCLK Falling Edge.
t
2
5
25 ns max
RFS
Low to Data Valid Delay.
t
3
t
CLK IN HI
ns nom SCLK High Pulse Width.
t
4
t
CLK IN LO
ns nom SCLK Low Pulse Width.
t
5
5
20 ns max SCLK Rising Edge to Data Valid Delay.
t
6
40 ns max
SCLK Rising Edge to
RFS
Delay.
t
7
6
50 ns max Bus Relinquish Time after Rising Edge of SCLK.
t
8
0 ns min
TFS
Low to SCLK Falling Edge.
t
CLK IN
+ 50 ns max
t
9
0 ns min
Data Valid to
TFS
Falling Edge Setup Time (A2 Address Bit).
t
10
20 ns min Data Valid to SCLK Falling Edge Setup Time.
t
11
10 ns min Data Valid to SCLK Falling Edge Hold Time.
t
12
20 ns min
TFS
to SCLK Falling Edge Hold Time.
External Clocking Mode
t
13
20 ns min
RFS
Low to SCLK Falling Edge Setup Time.
t
14
5
40 ns max
RFS
Low to Data Valid Delay.
t
15
50 ns min SCLK High Pulse Width.
t
16
50 ns min SCLK Low Pulse Width.
t
17
5
35 ns max SCLK Rising Edge to Data Valid Delay.
t
18
20 ns min
RFS
to SCLK Falling Edge Hold Time.
t
19
6
50 ns max
Bus Relinquish Time after Rising Edge of
RFS
.
t
19A
6
90 ns max Bus Relinquish Time after Rising Edge of SCLK.
t
20
20 ns min
TFS
Low to SCLK Falling Edge Setup Time.
t
21
10 ns min Data Valid to SCLK Falling Edge Setup Time.
t
22
15 ns min Data Valid to SCLK Falling Edge Hold Time.
t
23
40 ns min
TFS
to SCLK Falling Edge Hold Time.
1
Sample tested at −25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 10 to Figure 13.
3
The AD7890 is production tested with f
CLK IN
at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
4
Specified using 10% and 90% points on waveform of interest.
5
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
TO OUTPUT
PIN
2.1V
1.6mA
200µA
50pF
01357-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
