AD7890BRZ-4REEL Datasheet AD7890ARZ-10, AD7890ANZ-4, AD7890BRZ-2 | P19-P21

AD7890

Rev. C | Page 18 of 28

Write Operation

Figure 11 shows a write operation to the control register of the

AD7890. The

TFS

input is taken low to indicate to the part that

a serial write is about to occur.

TFS

going low initiates the SCLK

output and this is used to clock data out of the processors serial

port and into the control register of the AD7890. The AD7890

control register requires only five bits of data. These are loaded

on the first five clock cycles of the serial clock with data on all

subsequent clock cycles being ignored. However, the part

requires six serial clock cycles to load data to the control

on the falling edge of SCLK.

EXTERNAL CLOCKING MODE

The AD7890 is configured for its external clocking mode by

tying the SMODE pin of the device to a logic high. In this

mode, SCLK and

RFS

of the AD7890 are configured as inputs.

This external-clocking mode is designed for direct interface to

systems, which provide a serial clock output which is

synchronized to the serial data output including

microcontrollers such as the 80C51, 87C51, 68HC11, and

68HC05, and most digital signal processors.

Read Operation

Figure 12 shows the timing diagram for reading from the

AD7890 in the external clocking mode.

RFS

goes low to access

data from the AD7890. The serial clock input does not have to be

continuous. The serial data can be accessed in a number of bytes.

However,

RFS

must remain low for the duration of the data

transfer operation. Once again, 16th bits of data are transmitted

with one leading zero, followed by the three address bits in the

control register, followed by the 12-bit conversion result starting

with the MSB. If

RFS

goes low during the high time of SCLK,

the leading zero is clocked out from the falling edge of

RFS

(as

per Figure 12). If

RFS

goes low during the low time of SCLK,

the leading zero is clocked out on the next rising edge of SCLK.

This ensures that, regardless of whether

RFS

goes low during a

high time or low time of SCLK, the leading zero is valid on the

first falling edge of SCLK after

RFS

goes low, provided t

and t

are adhered to. Serial data is clocked out of the device on the

rising edge of SCLK and is valid on the falling edge of SCLK. At

the end of the read operation, the DATA OUT line is three-stated

by a rising edge on either the SCLK or

RFS

inputs, whichever

occurs first. If a serial read from the output register is in progress

when conversion is complete, the updating of the output register is

deferred until the serial data read is complete and

RFS

returns high.

Write Operation

Figure 13 shows a write operation to the control register of the

AD7890. As with self-clocking mode, the

TFS

input goes low to

indicate to the part that a serial write is about to occur. As before,

the AD7890 control register requires only five bits of data. These

are loaded on the first five clock cycles of the serial clock; data on all

subsequent clock cycles are ignored. However, the part requires six

serial clocks to load data to the control register. Serial data to be

written to the AD7890 must be valid on the falling edge of SCLK.

RFS (I)

SCLK (I)

DATA OUT (O)

NOTES:

1. (I) SIGNIFIES AN INPUT.

2. (O) SIGNIFIES AN OUTPUT.

THREE-STATE

LEADING

ZERO

DB10 DB0DB11A2 A1 A0

19A

01357-012

Figure 12. External Clocking (Slave) Mode Output Register Read

TFS (I)

SCLK (I)

DATA IN (I)

NOTES:

1. (I) SIGNIFIES AN INPUT.

2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

A2 A1 A0 CONV STBY

DON’T

CARE

DON’T

CARE

DON’T

CARE

01357-013

Figure 13. External Clocking (Slave) Mode Control Register Write

AD7890

Rev. C | Page 19 of 28

SIMPLIFYING THE INTERFACE

To minimize the number of interconnect lines to the AD7890,

the user can connect the

RFS

and

TFS

lines of the AD7890

together and read and write from the part simultaneously. In

this case, new control register data should be provided on the

DATA IN line selecting the input channel and possibly

providing a conversion start command while the part provides

the result from the conversion just completed on the

DATA OUT line.

In the self-clocking mode, this means that the part provides all

the signals for the serial interface. It does require that the

microprocessor has the data to be written to the control register

available in its output register when the part brings the

TFS

line

low. In the external clocking mode, it means that the user only

has to supply a single frame synchronization signal to control

both the read and write operations.

Care must be taken with this scheme that the read operation is

completed before the next conversion starts, if the user wants to

obtain optimum performance from the part. In the case of the

software conversion start, the conversion command is written

to the control register on the sixth serial clock edge. However,

the read operation continues for another 10 serial clock cycles.

To avoid reading during the sampling instant or during

conversion, the user should ensure that the internal pulse width

is sufficiently long (by choosing C

EXT

) so that the read operation

is completed before the next conversion sequence begins.

Failure to do this results in significantly degraded performance

from the part, both in terms of signal-to-noise ratio and dc

parameters. In the case of a hardware conversion start, the user

should ensure that the delay between the sixth falling edge of

the serial clock in the write operation and the next rising edge

CONVST

is greater than the internal pulse width.

AD7890

Rev. C | Page 20 of 28

MICROPROCESSOR/MICROCONTROLLER INTERFACE

The AD7890’s flexible serial interface allows for easy

connection to the serial ports of DSP processors and

microcontrollers. Figure 14 through Figure 17 show the

AD7890 interfaced to a number of different microcontrollers

and DSP processors. In some of the interfaces shown, the

AD7890 is configured as the master in the system, providing

the serial clock and frame sync for the read operation while in

others it acts as a slave with these signals provided by the

microprocessor.

AD7890 TO 8051 INTERFACE

Figure 14 shows an interface between the AD7890 and the

8xC51 microcontroller. The AD7890 is configured for its

external clocking mode while the 8xC51 is configured for its

Mode 0 serial interface mode. The diagram shown in Figure 14

makes no provisions for monitoring when conversion is

complete on the AD7890 (assuming hardware conversion start

is used). To monitor the conversion time on the AD7890, a

scheme, such as the scheme outlined with

CONVST

in the

Simplifying the Interface section, can be used. This can be

implemented in two ways. One is to connect the

CONVST

line

to another parallel port bit, which is configured as an input.

This port bit can then be polled to determine when conversion is

complete. An alternative is to use an interrupt driven system where

the

CONVST

line is connected to the

INT1

input of the 8xC51.

Since the 8xC51 contains only one serial data line, the DATA

OUT and DATA IN lines of the AD7890 must be connected

together. This means that the 8xC51 cannot communicate with

the output register and control register of the AD7890 at the

same time. The 8xC51 outputs the LSB first in a write operation

so care should be taken in arranging the data, which is to be

transmitted to the AD7890. Similarly, the AD7890 outputs the

MSB first during a read operation while the 8xC51 expects the

LSB first. Therefore, the data that is to be read into the serial

port needs to be rearranged before the correct data word from

the AD7890 is available in the microcontroller.

The serial clock rate from the 8xC51 is limited to significantly

less than the allowable input serial clock frequency with which

the AD7890 can operate. As a result, the time to read data from

the part is actually longer than the conversion time of the part.

This means that the AD7890 cannot run at its maximum

throughput rate when used with the 8xC51.

SMODE

RFS

TFS

DATA OUT

DATA IN

SCLK

P1.0

P1.1

P3.0

P3.1

AD7890

8xC51

01357-014

Figure 14. AD7890 to 8xC51 Interface

AD7890 TO 68HC11 INTERFACE

An interface circuit between the AD7890 and the 68HC11

microcontroller is shown in Figure 15. For the interface shown,

the AD7890 is configured for its external clocking mode while

the 68HC11’s SPI port is used and the 68HC11 is configured in

its single-chip mode. The 68HC11 is configured in the master

mode with its CPOL bit set to a Logic 0 and its CPHA bit set to

a Logic 1.

As with the previous interface, there are no provisions for

monitoring when conversion is complete on the AD7890. To

monitor the conversion time on the AD7890, a scheme, such as

the scheme outlined with

CONVST

in the Simplifying the

Interface section, can be used. This can be implemented in two

ways. One is to connect the

CONVST

line to another parallel

port bit, which is configured as an input. This port bit can then

be polled to determine when conversion is complete. An alternative

is to use an interrupt driven system in which case the

CONVST

line should be connected to the

IRQ

input of the 68HC11.

SMODE

RFS

TFS

DATA OUT

DATA IN

SCLK

PC0

PC1

SCK

MISO

MOSI

68HC11

AD7890

1357-015

Figure 15. AD7890 to 68HC11 Interface

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD7890BRZ-4REEL

Mfr. #:

Buy AD7890BRZ-4REEL

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC LC2MOS 8CH 12B Data Acquisition System

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AD7890BRZ-4REEL

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