AD7890BRZ-4REEL Datasheet AD7890ARZ-10, AD7890ANZ-4, AD7890BRZ-2 | P13-P15

AD7890

Rev. C | Page 12 of 28

Table 4. Ideal Input/Output Code Table for the AD7890-10

Analog Input

Digital Output Code Transition

+FSR/2 − 1 LSB

(9.995117 V) 011 . . . 110 to 011 . . . 111

+FSR/2 − 2 LSBs (9.990234 V) 011 . . . 101 to 011 . . . 110

+FSR/2 − 3 LSBs (9.985352 V) 011 . . . 100 to 011 . . . 101

AGND + 1 LSB (0.004883 V) 000 . . . 000 to 000 . . . 001

AGND (0.000000 V) 111 . . . 111 to 000 . . . 000

AGND − 1 LSB (−0.004883 V) 111 . . . 110 to 111 . . . 111

−FSR/2 + 3 LSBs (−9.985352 V) 100 . . . 010 to 100 . . . 011

−FSR/2 + 2 LSBs (−9.990234 V) 100 . . . 001 to 100 . . . 010

−FSR/2 + 1 LSB (−9.995117 V) 100 . . . 000 to 100 . . . 001

FSR is full-scale range and is 20 V with REF IN = 2.5 V.

1 LSB = FSR/4096 = 4.883 mV with REF IN = 2.5 V.

AD7890-4 Analog Input

Figure 5 shows the analog input section for the AD7890-4. The

analog input range for each of the analog inputs is 0 to 4.096 V

into an input resistance of typically 15 kΩ. This input is benign

with no dynamic charging currents with the resistor attenuator

stage followed by the multiplexer and in cases where MUX OUT is

connected to SHA IN this is followed by the high input

impedance stage of the track/hold amplifier. The designed code

transitions occur on successive integer LSB values (such as:

1 LSB, 2 LSBs, 3 LSBs . . . ). Output coding is straight (natural)

binary with 1 LSB = FSR/4096 = 4.096 V/4096 = 1 mV. The

ideal input/output transfer function is shown in Table 5.

2.5V

REFERENCE

6kΩ

2kΩ

200Ω

9.38kΩ

AD7890-4

REF OUT/

REF IN

AGND

INX

EQUIVALENT ON-RESISTANCE OF MULTIPLEXER

MUX OUT

TO ADC

REFERENCE

CIRCUITRY

01357-005

Figure 5. AD7890-4 Analog Input Structure

Table 5. Ideal Input/Output Code Table for the AD7890-4

Analog Input

Digital Output Code Transition

+FSR − 1 LSB

(4.095 V) 111 . . . 110 to 111 . . . 111

+FSR − 2 LSBs (4.094 V) 111 . . . 101 to 111 . . . 110

+FSR − 3 LSBs (4.093 V) 111 . . . 100 to 111 . . . 101

AGND + 3 LSBs (0.003 V) 000 . . . 010 to 000 . . . 011

AGND + 2 LSBs (0.002 V) 000 . . . 001 to 000 . . . 010

AGND + 1 LSB (0.001 V) 000 . . . 000 to 000 . . . 001

FSR is full-scale range and is 4.096 V with REF IN = 2.5 V.

1 LSB = FSR/4096 = 1 mV with REF IN = 2.5 V.

AD7890-2 Analog Input

The analog input section for the AD7890-2 contains no biasing

resistors and the selected analog input connects to the multi-

plexer and, in cases where MUX OUT is connected to SHA IN,

this is followed by the high input impedance stage of the track/

hold amplifier. The analog input range is, therefore, 0 V to 2.5 V

into a high impedance stage with an input current of less than

50 nA. The designed code transitions occur on successive

integer LSB values (such as: l LSB, 2 LSBs, 3 LSBs . . . FS-1

LSBs). Output coding is straight (natural) binary with 1 LSB =

FSR/4096 = 2.5 V/4096 = 0.61 mV. The ideal input/output

transfer function is shown in Table 6.

Table 6. Ideal Input/Output Code Table for the AD7890-2

Analog Input

Digital Output Code Transition

+FSR − 1 LSB

(2.499390 V) 111 . . . 110 to 111 . . . 111

+FSR − 2 LSBs (2.498779 V) 111 . . . 101 to 111 . . . 110

+FSR − 3 LSBs (2.498169 V) 111 . . . 100 to 111 . . . 101

AGND + 3 LSBs (0.001831 V) 000 . . . 010 to 010 . . . 011

AGND + 2 LSBs (0.001221 V) 000 . . . 001 to 001 . . . 010

AGND + 1 LSB (0.000610 V) 000 . . . 000 to 000 . . . 001

FSR is full-scale range and is 2.5 V with REF IN = 2.5 V.

1 LSB = FSR/4096 = 0.61 mV with REF IN = 2.5 V.

TRACK/HOLD AMPLIFIER

The SHA IN input on the AD7890 connects directly to the input

stage of the track/hold amplifier. This is a high impedance input

with input leakage currents of less than 50 nA. Connecting the

MUX OUT pin directly to the SHA IN pin connects the

multiplexer output directly to the track/hold amplifier. The input

voltage range for this input is 0 V to 2.5 V. If external circuitry is

connected between MUX OUT and SHA IN, then the user must

ensure that the input voltage range to the SHA IN input is 0 V to

2.5 V to ensure that the full dynamic range of the converter is

utilized.

The track/hold amplifier on the AD7890 allows the ADC to

accurately convert an input sine wave of full-scale amplitude to

12-bit accuracy. The input bandwidth of the track/hold is

greater than the Nyquist rate of the ADC even when the ADC is

operated at its maximum throughput rate of 117 kHz (for example,

the track/hold can handle input frequencies in excess of 58 kHz).

The track/hold amplifier acquires an input signal to 12-bit

accuracy in less than 2 μs. The operation of the track/hold is

essentially transparent to the user. The track/hold amplifier

goes from its tracking mode to its hold mode at the start of

conversion. The start of conversion is the rising edge of

CONVST

(assuming the internal pulse has timed out) for

hardware conversion starts and for software conversion starts is

the point where the internal pulse is timed out. The aperture

time for the track/hold (for example, the delay time between the

external

CONVST

signal and the track/hold actually going into

hold) is typically 15 ns. For software conversion starts, the time

depends on the internal pulse widths. Therefore, for software

conversion starts, the sampling instant is not very well defined.

For sampling systems which require well defined, equidistant

sampling, it may not be possible to achieve optimum performance

from the part using the software conversion start. At the end of

AD7890

Rev. C | Page 13 of 28

conversion, the part returns to its tracking mode. The acquisition

time of the track/ hold amplifier begins at this point.

REFERENCE

The AD7890 contains a single reference pin, labeled REF OUT/

REF IN, which either provides access to the part’s own 2.5 V

reference or to which an external 2.5 V reference can be connected

to provide the reference source for the part. The part is specified

with a 2.5 V reference voltage. Errors in the reference source results

in gain errors in the AD7890’s transfer function and adds to the

specified full-scale errors on the part. On the AD7893-10, it also

results in an offset error injected in the attenuator stage.

The AD7890 contains an on-chip 2.5 V reference. To use this

reference as the reference source for the AD7890, simply connect a

0.1 μF disc ceramic capacitor from the REF OUT/REF IN pin to

AGND. The voltage which appears at this pin is internally buffered

before being applied to the ADC. If this reference is required for

use external to the AD7890, it should be buffered as the source

impedance of this output is 2 kΩ nominal. The tolerance on the

internal reference is ±10 mV at 25°C with a typical temperature

coefficient of 25 ppm/°C and a maximum error over temperature

of ±25 mV.

If the application requires a reference with a tighter tolerance or

the AD7890 needs to be used with a system reference, then the

user has the option of connecting an external reference to this

REF OUT/REF IN pin. The external reference effectively

overdrives the internal reference and thus provides the reference

source for the ADC. The reference input is buffered, but has a

nominal 2 kΩ resistor connected to the AD7890’s internal

reference. Suitable reference sources for the AD7890 include the

AD680, AD780, and REF-43 precision 2.5 V references.

TIMING AND CONTROL

The AD7890 is capable of two interface modes, selected by the

SMODE input. The first of these is a self-clocking mode where

the part provides the frame sync, serial clock, and serial data at

the end of conversion. In this mode the serial clock rate is

determined by the master clock rate of the part (at the CLK IN

input). The second mode is an external clocking mode where

the user provides the frame sync and serial clock signals to obtain

the serial data from the part. In this second mode, the user has

control of the serial clock rate up to a maximum of 10 MHz. The

two modes are discussed in the Serial Interface section.

The part also provides hardware and software conversion start

features. The former provides a well-defined sampling instant

with the track/hold going into hold on the rising edge of the

CONVST

signal. For the software conversion start, a write to

the CONV bit to the control register initiates the conversion

sequence. However, for the software conversion start an internal

pulse has to time out before the input signal is sampled. This

pulse, plus the difficulty in maintaining exactly equal delays

between each software conversion start command, means that

the dynamic performance of the AD7890 may have difficulty

meeting specifications when used in software conversion start

mode. The AD7890 provides separate channel select and

conversion start control. This allows the user to optimize the

throughput rate of the system. Once the track/hold has gone into

hold mode, the input channel can be updated and the input voltage

can settle to the new value while the present conversion is in

progress.

Assuming the internal pulse has timed out before the

CONVST

pulse is exercised, the conversion consists of 14.5 master clock

cycles. In the self-clocking mode, the conversion time is defined

as the time from the rising edge of

CONVST

to the falling edge

RFS

(for example, when the device starts to transmit its

conversion result). This time includes the 14.5 master clock

cycles plus the updating of the output register and delay time in

outputting the

RFS

signal, resulting in a total conversion time of

5.9 μs maximum. Figure 6 shows the conversion timing for the

AD7890 when used in the self-clocking (master) mode with

hardware

CONVST

. The timing diagram assumes that the

internal pulse is not active when the

CONVST

signal goes high.

To ensure this, the channel address to be converted should be

selected by writing to the control register prior to the

CONVST

pulse. Sufficient setup time should be allowed between the

control register write and the

CONVST

to ensure that the internal

pulse has timed out. The duration of the internal pulse (and hence

the duration of setup time) depends on the value of C

EXT

TRACK/HOLD GOES

INTO THE HOLD

THREE-STATE

NOTES:

1. (I) SIGNIFIES AN INPUT.

2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

DATA OUT (O)

SCLK (O)

RFS (O)

CONVST (I)

CONVERT

01357-006

Figure 6. Self-Clocking (Master) Mode Conversion Sequence

AD7890

Rev. C | Page 14 of 28

When using the device in the external-clocking mode, the

output register can be read at any time and the most up-to-date

conversion result is obtained. However, reading data from the

output register or writing data to the control register during

conversion or during the 500 ns prior to the next

CONVST

results in reduced performance from the part. A read operation

to the output register has the most effect on performance with

the signal-to-noise ratio likely to degrade, especially when

higher serial clock rates are used while the code flicker from the

part also increases (see the Performance section).

Figure 7 shows the timing and control sequence required to

obtain optimum performance from the part in the external

clocking mode. In the sequence shown, conversion is initiated

on the rising edge of

CONVST

and new data is available in the

output register of the AD7890 5.9 μs later. Once the read

operation has taken place, a further 500 ns should be allowed

before the next rising edge of

CONVST

to optimize the settling

of the track/hold before the next conversion is initiated.

The diagram shows the read operation and the write operation

taking place in parallel. On the sixth falling edge of SCLK in the

write sequence the internal pulse is initiated. Assuming MUX OUT

is connected to SHA IN, 2 μs are required between this sixth

falling edge of SCLK and the rising edge of

CONVST

to allow

for the full acquisition time of the track/hold amplifier. With

the serial clock rate at its maximum of 10 MHz, the achievable

throughput rate for the part is 5.9 μs (conversion time) plus 0.6

μs (six serial clock pulses before internal pulse is initiated) plus

2 μs (acquisition time). This results in a minimum throughput

time of 8.5 μs (equivalent to a throughput rate of 117 kHz). If

the part is operated with a slower serial clock, it affects the

achievable throughput rate for optimum performance.

RFS

TFS

500ns MIN

CONVST

SCLK

NEXT CONVERSION

START COMMAND

CONVERSION IS

INITIATED AND

TRACK/HOLD GOES

INTO HOLD

CONVERSION

ENDS 5.9µs

LATER

SERIAL READ

AND WRITE

OPERATIONS

READ AND WRITE

OPERATIONS SHOULD END

500ns PRIOR TO NEXT

RISING EDGE OF CONVST

CONVERT

01357-007

Figure 7. External Clocking (Slave) Mode Timing Sequence for Optimum Performance

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AD7890BRZ-4REEL

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC LC2MOS 8CH 12B Data Acquisition System

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AD7890BRZ-4REEL

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