AD7890BRZ-4REEL Datasheet AD7890ARZ-10, AD7890ANZ-4, AD7890BRZ-2 | P16-P18

AD7890

Rev. C | Page 15 of 28

In the self-clocking mode, the AD7890 indicates when

conversion is complete by bringing the

RFS

line low and

initiating a serial data transfer. In the external clocking mode,

there is no indication of when conversion is complete. In many

applications, this is not a problem as the data can be read from

the part during conversion or after conversion. However,

applications that seek to achieve optimum performance from

the AD7890 has to ensure that the data read does not occur

during conversion or during 500 ns prior to the rising edge

CONVST

This can be achieved in either of two ways. The first is to ensure

in software that the read operation is not initiated until 5.9 μs

after the rising edge of

CONVST

. This is only possible if the

software knows when the

CONVST

command is issued. The

second scheme would be to use the

CONVST

signal as both the

conversion start signal and an interrupt signal. The simplest

way to do this is to generate a square wave signal for

CONVST

with high and low times of 5.9 μs (see Figure 8). Conversion is

initiated on the rising edge of

CONVST

. The falling edge of

CONVST

occurs 5.9 μs later and can be used as either an active

low or falling edge-triggered interrupt signal to tell the

processor to read the data from the AD7890. Provided the read

operation is completed 500 ns before the rising edge of

CONVST

, the AD7890 operates to specification.

This scheme limits the throughput rate to 11.8 μs minimum.

However, depending upon the response time of the

microprocessor to the interrupt signal and the time taken by the

processor to read the data, this may be the fastest which the

system could have operated. In any case, the

CONVST

signal

does not have to have a 50:50 duty cycle. This can be tailored to

optimize the throughput rate of the part for a given system.

Alternatively, the

CONVST

signal can be used as a normal

narrow pulse width. The rising edge of

CONVST

can be used as

an active high or rising edge-triggered interrupt. A software

delay of 5.9 μs can then be implemented before data is read

from the part.

NEXT CONVST

RISING EDGE

CONVERSION IS

INITIATED AND

TRACK/HOLD GOES

INTO HOLD

CONVERSION

ENDS 5.9µs

LATER

MICROPROCESSOR

INT SERVICE

OR POLLING

ROUTINE

SERIAL READ

AND WRITE

OPERATIONS

READ AND WRITE

OPERATIONS SHOULD

END 500ns PRIOR

TO NEXT RISING

EDGE OF CONVST

CONVERT

500ns MIN

RFS

TFS

CONVST

SCLK

01357-008

Figure 8.

CONVST

Used as Status Signal in External Clocking Mode

AD7890

Rev. C | Page 16 of 28

EXT

FUNCTIONING

The C

EXT

input on the AD7890 provides a means of determining

how long after a new channel address is written to the part that

a conversion can take place. The reason behind this is two-fold.

First, when the input channel to the AD7890 is changed, the

input voltage on this new channel is likely to be very different

from the previous channel voltage. Therefore, the part’s track/

hold has to acquire the new voltage before an accurate

conversion can take place. An internal pulse delays any

conversion start command (as well as the signal to send the

track/hold into hold) until after this pulse has timed out.

The second reason is to allow the user to connect external

antialiasing or signal conditioning circuitry between the

MUX OUT pin and the SHA IN pin. This external circuitry

introduces extra settling time into the system. The C

EXT

provides a means for the user to extend the internal pulse to

take this extra settling time into account. Effectively varying the

value of the capacitor on the C

EXT

pin varies the duration of the

internal pulse. Figure 9 shows the relationship between the

value of the C

EXT

capacitor and the internal delay.

0 250 500 750 1000 1250 1500 1750 2000

01357-009

INTERNAL PULSE WIDTH (µs)

EXT

CAPACITANCE (pF)

= +85°C

= –40°C

= +25°C

Figure 9. Internal Pulse Width vs. C

EXT

The duration of the internal pulse can be seen on the C

EXT

pin.

The C

EXT

pin goes from a low to a high when a serial write to

the part is initiated (on the falling edge of

TFS

). It starts to

discharge on the sixth falling edge of SCLK in the serial write

operation. Once the C

EXT

pin has discharged to crossing its

nominal trigger point of 2.5 V, the internal pulse is timed out.

The internal pulse is initiated each time a write operation to the

control register takes place. As a result, the pulse is initiated and

the conversion process delayed for all software conversion start

commands. For hardware conversion start, it is possible to

separate the conversion start command from the internal pulse.

If the multiplexer output (MUX OUT) is connected directly to

the track/hold input (SHA IN), then no external settling has to

be taken into account by the internal pulse width. In applications

where the multiplexer is switched and conversion is not

initiated until more than 2 μs after the channel is changed (as is

possible with a hardware conversion start), the user does not

have to worry about connecting any capacitance to the

EXT

pin. The 2 μs equates to the track/hold acquisition time of

the AD7890. In applications where the multiplexer is switched

and conversion is initiated at the same time (such as with a

software conversion start), a 120 pF capacitor should be

connected to C

EXT

to allow for the acquisition time of the

track/hold before conversion is initiated.

If external circuitry is connected between the MUX OUT pin

and SHA IN pin, then the extra settling time introduced by this

circuitry must be taken into account. In the case where the

multiplexer change command and the conversion start

command are separated, they need to be separated by greater

than the acquisition time of the AD7890 plus the settling time

of the external circuitry if the user does not have to worry about

the C

EXT

capacitance. In applications where the multiplexer is

switched and conversion is initiated at the same time (such as

with a software conversion start), the capacitor on C

EXT

needs to

allow for the acquisition time of the track/hold and the settling

time of the external circuitry before conversion is initiated.

AD7890

Rev. C | Page 17 of 28

SERIAL INTERFACE

The AD7890’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers, and digital signal processors.

A serial read to the AD7890 accesses data from the output

writes data to the control register via the DATA IN line.

Two different modes of operation are available, optimized for

different types of interface where the AD7890 can act either as

master in the system (it provides the serial clock and data

framing signal) or acts as slave (an external serial clock and

framing signal can be provided to the AD7890). The former is

self-clocking mode while the latter is external clocking mode.

SELF-CLOCKING MODE

The AD7890 is configured for its self-clocking mode by tying

the SMODE pin of the device to a logic low. In this mode, the

AD7890 provides the serial clock signal and the serial data

framing signal used for the transfer of data from the AD7890.

This self-clocking mode can be used with processors that allow

an external device to clock their serial port, including most

digital signal processors.

Read Operation

Figure 10 shows a timing diagram for reading from the AD7890

in the self-clocking mode. At the end of conversion,

RFS

goes

low and the serial clock (SCLK) and serial data (DATA OUT)

outputs become active. Sixteen bits of data are transmitted with

one leading zero, followed by the three address bits of the

control register, followed by the 12-bit conversion result starting

with the MSB. Serial data is clocked out of the device on the

rising edge of SCLK and is valid on the falling edge of SCLK.

The

RFS

output remains low for the duration of the 16 clock

cycles. On the 16

rising edge of SCLK, the

RFS

output is driven

high and DATA OUT is disabled.

RFS (O)

SCLK (O)

DATA OUT (O)

THREE-STATE

LEADING

ZERO

DB0DB10DB11A2 A1 A0

NOTES:

1. (I) SIGNIFIES AN INPUT.

2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

01357-010

Figure 10. Self-Clocking (Master) Mode Output Register Read

TFS (I)

SCLK (O)

DATA IN (I)

NOTES:

1. (I) SIGNIFIES AN INPUT.

2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

A2 A1 A0 CONV STBY

DON’T

CARE

DON’T

CARE

DON’T

CARE

01357-011

Figure 11. Self-Clocking (Master) Mode Control Register Write

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD7890BRZ-4REEL

Mfr. #:

Buy AD7890BRZ-4REEL

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC LC2MOS 8CH 12B Data Acquisition System

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New from this manufacturer.

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AD7890BRZ-4REEL

AD7890BRZ-4REEL

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