AD7890
Rev. C | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
REF OUT/REF I
CONVST
TFS
RFS
DATA OUT
DATA IN
V
DD
V
IN8
V
IN7
V
IN6
V
IN5
V
IN4
V
IN3
V
IN2
V
IN1
AD7890
TOP VIEW
(Not to Scale)
AGND
AGND
SHA IN
MUX OUT
DGND
CLK IN
SCLK
C
EXT
SMODE
01357-003
Figure 3. Pin Configuration
Table 2. Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND Analog Ground. Ground reference for track/hold, comparator, and DAC.
2 SMODE
Control Input. Determines whether the part operates in its external clocking (slave) or self-clocking (master)
serial mode. With SMODE at a logic low, the part is in its self-clocking serial mode with
RFS and SCLK as
outputs. This self-clocking mode is useful for connection to shift registers or to serial ports of DSP processors.
With SMODE at a logic high, the part is in its external clocking serial mode with SCLK and
RFS as inputs. This
external clocking mode is useful for connection to the serial port of microcontrollers, such as the 8xC51 and
the 68HCxx, and for connection to the serial ports of DSP processors.
3 DGND Digital Ground. Ground reference for digital circuitry.
4 C
EXT
External Capacitor. An external capacitor is connected to this pin to determine the length of the internal pulse
(see the Control Register section). Larger capacitances on this pin extend the pulse to allow for settling time
delays through an external antialiasing filter or signal conditioning circuitry.
5
CONVST Convert Start. Edge-triggered logic input. A low-to-high transition on this input puts the track/hold into hold
and initiates conversion if the internal pulse has timed out (see the Control Register section). If the internal
pulse is active when the
CONVST goes high, the track/hold does not proceed to hold until the pulse times out.
If the internal pulse times out when CONVST goes high, the rising edge of CONVST drives the track/hold into
hold and initiates conversion.
6 CLK IN
Clock Input. An external TTL-compatible clock is applied to this input pin to provide the clock source for the
conversion sequence. In the self-clocking serial mode, the SCLK output is derived from this CLK IN pin.
7 SCLK
Serial Clock Input. In the external clocking (slave) mode (see the Serial Interface section), this is an externally
applied serial clock used to load serial data to the control register and to access data from the output register.
In the self-clocking (master) mode, the internal serial clock, which is derived from the clock input (CLK IN),
appears on this pin. Once again, it is used to load serial data to the control register and to access data from the
output register.
8
TFS Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the falling edge of
this signal.
9
RFS Receive Frame Synchronization Pulse. In the external clocking mode, this pin is an active low logic input with
RFS provided externally as a strobe or framing pulse to access serial data from the output register. In the self-
clocking mode, it is an active low output, which is internally generated and provides a strobe or framing pulse
for serial data from the output register. For applications which require that data be transmitted and received at
the same time,
RFS and TFS should be connected together.
10 DATA OUT
Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three address
bits of the control register and the 12 bits of conversion data. Serial data is valid on the falling edge of SCLK for
sixteen edges after
RFS goes low. Output coding from the ADC is twos complement for the AD7890-10 and
straight binary for the AD7890-4 and AD7890-2.
11 DATA IN
Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first five bits of
serial data are loaded to the control register on the first five falling edges of SCLK after
TFS goes low. Serial data
on subsequent SCLK edges is ignored while
TFS remains low.
12 V
DD
Positive Supply Voltage, 5 V ± 5%.
13 MUX OUT
Multiplexer Output. The output of the multiplexer appears at this pin. The output voltage range from this
output is 0 V to 2.5 V for the nominal analog input range to the selected channel. The output impedance of this
output is nominally 3.5 kΩ. If no external antialiasing filter is required, MUX OUT should be connected to SHA IN.
