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ST7540
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P44
ST7540
Electrical cha
racteristics
13/44
5V V
oltage regulator
VDC
Linear regulator output
vol
t
a
g
e
0 < Io < 5
0mA
7.5V < V
CC
< 13.5V
-5%
5.05
+5%
V
3.3V V
olta
ge regulator
V
DD
Linear regulator output
vol
t
a
g
e
0 < Io < 5
0mA
7.5V < V
CC
< 13.5V
-5%
3.3
+5%
V
Other functions
T
RST
O
Reset time
See
Figure 23
;
Xtal = 16MHz
50
ms
T
WD
W
atch-dog pulse width
See
Figure 23
125
ns
T
WM
W
atch-dog pulse
period
Minimum v
alue.
See
Figure 23
250
ns
Maximum v
alue.
See
Figure 23
1490
ms
T
WO
W
atch-dog time out
See
Figure 23
1.5
s
T
OUT
TX time out
Control register bit 7
and bit 8
1
3
s
T
OFF
Time Out OFF time
Figure 22
125
ms
T
OFFD
RxTx 0->1 vs. time out
delay
Figure 22
20
µ
s
T
CD
Carrier detection time
selectable b
y register
Control register
bit 9 and bit10
Figure 14
500
1
3
5
µ
s
ms
ms
ms
T
DCD
CD_PD Propagation
delay
Figure 14
300
500
µ
s
M
CLK
Master clock output
selectable b
y register
Control register
bit 15 and bi
t 16
See
Ta
b
l e
1
2
fcloc
k
fcloc
k/2
fcloc
k/4
off
MHz
BA
UD
Baud rate
Control register
bit 3 and bit
4
See
Ta
b
l e
1
2
600
1200
2400
4800
Baud
T
ab
le 5. Electric
al characterist
ics
(continued)
(
V
DD
= +5V
,
V
CC
=+9 V
,
V
SS
= S
V
SS
= GND = 0V
,-40°C
≤
T
A
≤
85°C
, T
J
< 125°C
,
unless otherwise specified)
Symbol
Parameter
T
est condition
Min.
T
yp.
Max.
Unit
Electrical ch
aracteristics
ST7540
14/44
Figure 3.
PLI configurat
ion for P
A_OUT distortions measurement
Serial Interface
T
B
Baud rate Bit Time
(1/BA
UD)
Control register bit 3
and bit 4
(See
Figure 13
)
1667
833
417
208
µ
s
Ts
Setup time
see Figures 8, 9, 10, 11
& 12
5n
s
T
H
Hold time
see Figures 8, 9, 10, 11
& 12
2n
s
T
CR
CLR/T vs. REG_D
A
T
A
or RxTx
see Figures 8, 9, 10, 11
& 12
T
B
/4
T
CC
CLR/T vs. CLR/T
see Figures 8, 9, 10, 11
& 12
T
B
2*T
B
T
DS
Setup time
see Figures 8, 9, 10, 11
& 12
T
B
/4
T
B
/2
T
DH
Hold time
see Figures 8, 9, 10, 11
& 12
T
B
/4
T
B
/2
T
CRP
T
H
T
B
/2
1.
Not tested, guaranteed by design
T
ab
le 5. Electric
al characterist
ics
(continued)
(
V
DD
= +5V
,
V
CC
=+9 V
,
V
SS
= S
V
SS
= GND = 0V
,-40°C
≤
T
A
≤
85°C
, T
J
< 125°C
,
unless otherwise specified)
Symbol
Parameter
T
est condition
Min.
T
yp.
Max.
Unit
Vcc
10 k
Ω
2.7 k
Ω
5 k
Ω
150 pF
100 pF
1uF
30
Ω
PA
P
A_OUT
P
A_IN -
P
A_IN +
Measurement point
Vss
V
AC
= 2Vpp
V
DC
= 1.9
V
D03IN142
6
ST7540
Crystal resonator
and external clock
15/44
5
Crystal resonator and external c
lock
Figure 4.
External c
lock wa
veform
Figure 5.
Crystal Reso
nator
X2
SVss
Ex
t
e
r
n
al
C
lo
c
k
SWING
Ex
t
e
r
n
al
C
lo
c
k
OFFSET
X1
X2
D03IN1425A
32 pF
32 pF
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P44
ST7540
Mfr. #:
Buy ST7540
Manufacturer:
STMicroelectronics
Description:
Network Controller & Processor ICs FSK powerline transceiver
Lifecycle:
New from this manufacturer.
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