Block diagram ST7540
4/44
1 Block diagram
Figure 1. Block diagram
SERIAL
INTERFACE
CARRIER
DETECTION
PLL
CD/PD
RxD
CLR/T
REG/DATA
RxTx
TxD
Vdc
V
CC
PA_OUT
TX_OUT
Vsense
CL
RX_IN
TEST2
UART/SPI
TEST1 BU/THERM
X1 WD
RSTO MCLK
X2
DIGITAL
FILTER
FSK
DEMOD
IF
FILTER
TX
FILTER
FILTER
FILTER
BU
DAC
OSC
AGC
AMPL
TEST
ALC
PA
VREG
CURRENT
CONTROL
VOLTAGE
CONTROL
FSK
MODULATOR
TIME BASE
CONTROL
REGISTER
D03IN1407A
PA_IN-
+
-
PA_IN+
V
SS
VREG
V
DD
SV
SS
GND
ST7540 Pin settings
5/44
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection (top view)
2.2 Pin description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CD_PD
REG_DATA
GND
RxD
RxTx
TxD
BU/THERM
CLR/T
V
DD
MCLK
RSTO
UART/SPI
WD
PA_IN-
TEST2
TEST1
VDC
RX_IN
CL
Vsense
X2
X1_OSCIN
SV
SS
TX_OUT
PA_IN+
V
CC
V
SS
PA_OUT
Table 1. Pin description
Name Type Description
1 CD_PD Digital/Output
Carrier, preamble or frame header detect output.
"1" No carrier, preamble or frame header detected
"0" Carrier, preamble or frame header detected
2REG_DATA
Digital/Input
with internal pull-down
Mains or control register access selector
"1" - Control register access
"0" - Mains access
3 GND Supply Digital ground
4 RxD Digital/Output RX data output.
5 RxTx
Digital/Input
with internal pull-up
Rx or Tx mode selection input.
"1" - RX Session
"0" - TX Session
6TxD
Digital/Input
with internal pull-down
TX data input.
Pin settings ST7540
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7 BU/THERM Digital/Output
Band in use/Thermal Shutdown event detection output.
In Rx mode:
"1" Signal within the programmed band
"0" No signal within the programmed band
In Tx mode:
"1" - Thermal Shutdown event occurred
"0" - No Thermal Shutdown event occurred
(signal not latched)
8 CLR/T Digital/Output
Synchronous mains access clock or
control register access clock
9
V
DD
Supply/Power Digital supply voltage or 3.3V voltage regulator output
10 MCLK Digital/Output Master clock output
11 RSTO Digital/Output Power ON or watchdog reset output
12 UART/SPI
Digital/Input
with internal pull-down
Interface type:
“0” - Serial peripheral interface
“1” - UART interface
13 WD
Digital/Input
with internal pull-up
Watchdog input. The internal watchdog counter is
cleared on the falling edges.
14 PA_IN- Analog/Input Power line amplifier inverting input
15 PA_OUT Power/Output Power line amplifier output
16
V
SS
Supply Power analog ground
17
V
CC
Supply Power supply voltage
18 PA_IN+ Analog/Input Power line amplifier not inverting input
19 TX_OUT Analog/Output Small signal analog transmit output
20
SV
SS
Supply Analog signal ground
21 X1 Analog/Output Crystal oscillator output
22 X2 Analog/Input Crystal oscillator input - or external clock input
23
V
SENSE
(1)
Analog/Input Output voltage sensing input for the voltage control loop
24
CL
(2)
Analog/Input
Current limiting feedback.
A resistor between CL and SV
SS
sets the PLI current
limiting value. An integrated 80pF filtering input
capacitance is present on this pin.
25 RX_IN Analog/Input Receiving analog input
26 VDC Power 5V voltage regulator output
27 TEST1
Digital/Input
with internal pull-down
Test input. Must be connected to GND.
28 TEST2 Analog/Input
Test input. Must be connected SV
SS
1. Cannot be left floating
2. Cannot be left floating
Table 1. Pin description (continued)
Name Type Description

ST7540

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Network Controller & Processor ICs FSK powerline transceiver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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