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ST7540

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
ST7540 Functional description
19/44
6.5 Host processor interface
ST7540 exchanges data with the host processor through a serial interface.
The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged
using RxD, TxD and CLR/T lines.
Four are the ST7540 working modes:
● Data Reception
● Data Transmission
● Control Register Read
● Control Register Write
REG_DATA and RxTx lines are level sensitive inputs.
ST7540 features two type of Host Communication Interfaces:
● SPI
● UART
The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to “0” SPI
interface is selected while if UART/SPI pin is forced to “1” UART interface is selected. The
type of interface affects the Data Reception by setting the idle state of RxD line. When
ST7540 is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available on
mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the RxD
line is forced to “0” when UART/SPI pin is forced to ”0” or it is forced to “1” when UART/SPI
pin is forced to ”1”.
The UART interface allows to connect an UART compatible device while SPI interface
allows to connect an SPI compatible device. The allowed combinations of Host
Interface/ST7540 Mains Access are:
Table 9. Data and Control register access bits configuration
REG_DATA RxTx
Data Transmission 0 0
Data Reception 0 1
Control Register Read 1 1
Control Register Write 1 0
Table 10. Host interface / ST7540 mains access combinations
Host device
interface type
UART/SPI pin
Communication
mode
Mains access
Asynchronous Synchronous
UART “1” Transmission X
UART “1” Reception X
SPI “0” Transmission X
SPI “0” Reception X
Functional description ST7540
20/44
Figure 6. Synchronous and Asynchronous ST7540/Host Controller interfaces
ST7540 allows to interface the Host Controller using a five line interface (RxD,TxD,RxTx,
CLR/T, & REG_DATA) in case of Synchronous mains access or using a 3 line interface
(RxD,TxD & RxTx) in Asynchronous mains access. Since Control Register is not accessible
in Asynchronous mode, in this case REG_DATA pin must be tied to GND.
6.5.1 Communication between Host and ST7540
The Host can achieve the Mains access by selecting REG_DATA=”0” and the choice
between Data Transmission or Data Reception is performed by selecting RxTx line (if RxTx
=“1” ST7540 receives data from mains, if RxTx=”0” ST7540 transmits data over the mains).
Communication between Host and ST7540 is different in Asynchronous and Synchronous
mode:
● Asynchronous mode:
In Asynchronous Mode, data are exchanged without any data Clock reference. The
host controller has to recover the clock reference in receiving Mode and control the Bit
time in transmission mode.
If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7540 enters in an Idle
State. After Tcc time the modem starts providing received data on RxD line.
If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7540 enters in an
Idle State and transmission circuitry is switched on. After Tcc time the modem starts
transmitting data present on TxD line.
RxD
CLR/T
REG_DATA
RxTx
ST7540Host Controller
TxD
UART/Asynchronous
Data Interface
RxD
CLR/T
REG_DATA
RxTx
ST7540Host Controller
TxD
SPI/Synchronous
Data Interface
D03IN1415
ST7540 Functional description
21/44
● Synchronous mode:
In Synchronous Mode ST7540 is always the master of the communication and provides
the clock reference on CLR/T line. When ST7540 is in receiving mode an internal PLL
recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge.
When ST7540 is in transmitting mode the clock reference is internally generated and
TxD line is sampled on CLR/T rising Edge.
If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7540 enters in an Idle
State and CLR/T line is forced Low. After Tcc time the modem starts providing received
data on RxD line.
If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7540 enters in an
Idle State and transmission circuitry is switched on. After Tcc time the modem starts
transmitting data present on TxD line (Figure 8) .
Figure 7. Receiving and transmitting data/recovered clock timing
Figure 8. Data reception -> data transmission -> data reception
Transmitting Bit Synchronization
CLR/T
RxD
CLR/T
TxD
Receiving Bit Synchronization
T
S
T
H
D03IN1416
T
CC
T
DS
T
CR
T
CR
T
DH
T
S
T
H
T
B
T
CC
CLR_T
RxD
RxTx
TxD
REG_DATA
D03IN1402
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

ST7540

Mfr. #:
Buy ST7540
Manufacturer:
STMicroelectronics
Description:
Network Controller & Processor ICs FSK powerline transceiver
Lifecycle:
New from this manufacturer.
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