ST7540 Datasheet ST7540, ST7540TR | P22-P24

Functional description ST7540

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6.5.2 Control register access

The communication with ST7540 Control Register is always synchronous. The access is

achieved using the same lines of the Mains interface (RxD, TxD, RxTx and CLR/T) plus

REG_DATA Line.

With REG_DATA = 1 and RxTx = 0, the data present on TxD are loaded into the Control

edge).

In Normal Control Register mode (Control Register bit 21 = ”0”, see Ta bl e 1 2) if more than

24 bits are transferred to ST7540 only latest 24 bits are stored inside the Control Register. If

less than 24 bits are transferred to ST7540 the Control Register writing is aborted.

In order to avoid undesired Control Register writings caused by REG_DATA line fluctuations

(for example because of surge or burst on mains), in Extended Control Register mode

(Control Register bit 21 = ”1” see Tabl e 1 2 ) exactly 24 or 48 bits must be transferred to

ST7540 in order to properly write the Control Register, otherwise writing is aborted. If 24 bits

are transferred, only the first 24 Control Register bits (from 23 to 0) are written.

With REG_DATA = 1 and RxTx = 1, the content of the Control Register is sent on RxD port.

The Data on RxD are stable on CLR/T rising edges MSB First. In Normal Control Register

mode 24 bits are transferred from ST7540 to the Host. In Extended Control Register mode

24 or 48 bits are transferred from ST7540 to the Host depending on content of Control

transferred, see Ta b l e 1 2).

Figure 9. Data reception

➨ control register read ➨ data reception timing diagram

Figure 10. data reception

➨ control register write ➨ data reception timing diagram

CLR_T

RxD

REG_DATA

RxTx

D03IN1404

BIT23 BIT22

CLR_T

RxD

RxTx

TxD

REG_DATA

D03IN1403

BIT23 BIT22

ST7540 Functional description

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Figure 11. Data transmission ➨ control register read ➨ data reception timing diagram

Figure 12. Data transmission

➨ control register write ➨ data reception timing diagram

6.6 Receiving mode

The receive section is active when RxTx Pin =”1” and REG_DATA=0.

The input signal is read on RX_IN Pin using SV

as ground reference and then pre-filtered

by a Band pass Filter (62kHz max bandwidth at -3dB). The Pre-Filter can be inserted setting

one bit in the Control Register. The Input Stage features a wide dynamic range to receive

Signal with a Very Low Signal to Noise Ratio. The Amplitude of the applied waveform is

automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a

Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (14kHz

max at -3dB). The resulting signal is down-converted by a mixer using a sinewave generated

by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter)

improves the Signal to Noise ration before sending the signal to the FSK demodulator. The

FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital

filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal

Jitter. RxD Line is forced to “0” or “1” (according the UART/SPI pin level) when neither mark

or space frequencies are detected on RX_IN Pin.

Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have

a correct demodulation.

While ST7540 is in Receiving Mode (RxTx pin =”1”), the transmit circuitry, Power Line

Interface included, is turned off. This allows the device to achieve a very low current

consumption (5mA typ).

CLR_T

RxD

TxD

REG_DATA

RxTx

D03IN1405

BIT23 BIT22

CLR_T

TxD

RxD

REG_DATA

RxTx

D03IN1401

BIT23 BIT22

Functional description ST7540

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● Receiving Sensitivity Level Selection

It is possible to select the ST7540 Receiving Sensitivity Level by Control Register (see

Ta bl e 1 2 ) or setting to ‘1’ the TxD pin during reception phase (this condition overcomes

the control register setting the sensitivity equal to BU threshold). Increasing the device

sensitivity allows to improve the communication reliability when the ST7540 sensitivity

is the limiting factor.

● Synchronization Recovery System (PLL)

ST7540 embeds a Clock Recovery System to feature a Synchronous data exchange

with the Host Controller. The clock recovery system is realized by means of a second

order PLL. In Synchronous mode, data on the data line (RxD) are stable on CLR/T line

rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN

Range). The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock

condition RxD line is forced to “0” or “1” according to the UART/SPI pin level and CLR/T

is forced to “0” only if the Detection Method “Preamble Detection With Conditioning” is

selected.When PLL is in unlock condition it is sensitive to RxD Rising and Falling

Edges. The maximum number of transition required to reach the lock-in condition is 5.

When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the

CLR/T Jitter. ST7540 PLL is forced in the un-lock condition, when more than 32 equal

symbols are received.Due to the fact that the PLL, in lock-in condition, is sensitive only

to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL

into the un-lock condition.

Figure 13. ST7540 PLL lock-in range

● Carrier/Preamble Detection

The Carrier/Preamble Block is a digital Frequency detector Circuit.

It can be used to manage the MAINS access and to detect an incoming signal.

Two are the possible setting:

– Carrier Detection

– Preamble Detection

CLR/T

RxD

D03IN1417

LOCK-IN RANGE

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P44

ST7540

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