ST7540 Functional description
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Figure 20. Power line interface topology
Figure 21. Power line interface startup timing diagram
R1
ALC
VOLTAGE
LOOP
CURRENT
LOOP
Vsense
CL
R2
RCL
80pF typ.
TX_OUT
D03IN1422
Vcc
R3
R4
Vss
PA_OUT
-
+
PA_IN+
PA_IN-
Z1
Z2
AC LINE
T
ST
2.1V
0V
T
ALC
T
RXTX
RxTx
TX_OUT
STEP NUMBER 16 17 18 31
D03IN1408
Functional description ST7540
32/44
6.8 Control register
The ST7540 is a multi-channel and multifunction transceiver. An internal 24 or 48 Bits (in
Extended mode) Control Register allows to manage all the programmable parameters
(Table 1 2 ).
The programmable functions are:
Channel Frequency
Baud Rate
Deviation
Watchdog
Transmission Timeout
Frequency Detection Time
Detection Method
Mains Interfacing Mode
Output Clock
Sensitivity Mode
Input Pre-Filter
In addition to these functions the Extended mode provides 24 additional bits and others
functions:
Output Level Freeze
Frame Header Recognizes (one 16 bits header of or two 8 bits headers) with support to
Frame Length Bit count
ST7540 Functional description
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Table 12. Control register functions
Function Value Selection Note Default
0 to 2 Frequencies
Bit2 Bit1 Bit0
60 KHz
66 KHz
72 KHz
76 KHz
82.05 KHz
86 KHz
110 KHz
132.5 KHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
132.5 kHz
3 to 4 Baud rate
Bit 4 Bit 3
600
1,200
2,400
4,800
0
0
1
1
0
1
0
1
2400
5Deviation
Bit 5
0.5
1
0
1
0.5
6 Watchdog
Bit 6
Disabled
Enabled (1.5 s)
0
1
Enabled
7 to 8
Transmission
time out
Bit 8 Bit 7
Disabled
1 s
3 s
Not Used
0
0
1
1
0
1
0
1
1 sec
9 to 10
Frequency
detection time
Bit 10 Bit 9
500 µs
1 ms
3 ms
5 ms
0
0
1
1
0
1
0
1
1 ms
11 Reserved Do not force a different value 0

ST7540

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Network Controller & Processor ICs FSK powerline transceiver
Lifecycle:
New from this manufacturer.
Delivery:
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