a
AD7714
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Charge Balancing ADC
24 Bits No Missing Codes
0.0015% Nonlinearity
Five-Channel Programmable Gain Front End
Gains from 1 to 128
Can Be Configured as Three Fully Differential
Inputs or Five Pseudo-Differential Inputs
Three-Wire Serial Interface
SPI™, QSPI™, MICROWIRE™ and DSP Compatible
3 V (AD7714-3) or 5 V (AD7714-5) Operation
Low Noise (<150 nV rms)
Low Current (350␣ A typ) with Power-Down (5 A typ)
AD7714Y Grade:
+2.7 V to 3.3 V or +4.75 V to +5.25 V Operation
0.0010% Linearity Error
–40C to +105C Temperature Range
Schmitt Trigger on SCLK and DIN
Low Current (226␣ A typ) with Power-Down (4 A typ)
Lower Power Dissipation than Standard AD7714
Available in 24-Lead TSSOP Package
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
APPLICATIONS
Portable Industrial Instruments
Portable Weigh Scales
Loop-Powered Systems
Pressure Transducers
3 V/5 V, CMOS, 500 A
Signal Conditioning ADC
GENERAL DESCRIPTION†
The AD7714 is a complete analog front end for low-frequency
measurement applications. The device accepts low level signals
directly from a transducer and outputs a serial digital word. It
employs a sigma-delta conversion technique to realize up to 24
bits of no missing codes performance. The input signal is applied
to a proprietary programmable gain front end based around an
analog modulator. The modulator output is processed by an on-
chip digital filter. The first notch of this digital filter can be
programmed via the on-chip control register allowing adjust-
ment of the filter cutoff and settling time.
The part features three differential analog inputs (which can also
be configured as five pseudo-differential analog inputs) as well as a
differential reference input. It operates from a single supply (+3␣ V
or +5␣ V). The AD7714 thus performs all signal conditioning and
conversion for a system consisting of up to five channels.
The AD7714 is ideal for use in smart, microcontroller- or DSP-
based systems. It features a serial interface that can be configured
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
for three-wire operation. Gain settings, signal polarity and channel
selection can be configured in software using the serial port. The
AD7714 provides self-calibration, system calibration and back-
ground calibration options and also allows the user to read and
write the on-chip calibration registers.
CMOS construction ensures very low power dissipation, and the
power-down mode reduces the standby power consumption to
15␣ µW typ. The part is available in a 24-pin, 0.3 inch-wide, plastic
dual-in-line package (DIP); a 24-lead small outline (SOIC)
package, a 28-lead shrink small outline package (SSOP) and a
24-lead thin shrink small outline package (TSSOP).
PRODUCT HIGHLIGHTS
1. The AD7714Y offers the following features in addition to the
standard AD7714: wider temperature range, Schmitt trigger
on SCLK and DIN, operation down to 2.7 V, lower power
consumption, better linearity, and availability in 24-lead
TSSOP package.
2. The AD7714 consumes less than 500 µA (f
CLK IN
= 1␣ MHz)
or 1 mA (f
CLK IN
= 2.5␣ MHz) in total supply current, making
it ideal for use in loop-powered systems.
3. The programmable gain channels allow the AD7714 to ac-
cept input signals directly from a strain gage or transducer
removing a considerable amount of signal conditioning.
4. The AD7714 is ideal for microcontroller or DSP processor
applications with a three-wire serial interface reducing the num-
ber of interconnect lines and reducing the number of opto-
couplers required in isolated systems. The part contains
on-chip registers that allow control over filter cutoff, input gain,
channel selection, signal polarity and calibration modes.
5. The part features excellent static performance specifications
with 24-bit no missing codes, ±0.0015% accuracy and low
rms noise (140 nV). Endpoint errors and the effects of tem-
perature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.
†See page 39 for data sheet index.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
REF IN(+)
MCLK IN
MCLK OUT
A = 1–128
CHARGE
BALANCING
A/D CONVERTER
REF IN(–)
AD7714
BUFFER
AGND
BUFFER
SERIAL INTERFACE
AGND
DGND
REGISTER BANK
Σ-
MODULATOR
SYNC
STANDBY
DIGITAL FILTER
DV
DD
AV
DD
AV
DD
PGA
1mA
1mA
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
SWITCHING
MATRIX
CLOCK
GENERATION
SCLK
CS
DIN
DOUT
POL
DRDY
RESET
AD7714* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
AD7714 Evaluation Kit
DOCUMENTATION
Application Notes
AN-202: An IC Amplifier User’s Guide to Decoupling,
Grounding, and Making Things Go Right for a Change
AN-283: Sigma-Delta ADCs and DACs
AN-311: How to Reliably Protect CMOS Circuits Against
Power Supply Overvoltaging
AN-388: Using Sigma-Delta Converters-Part 1
AN-389: Using Sigma-Delta Converters-Part 2
AN-397: Electrically Induced Damage to Standard Linear
Integrated Circuits:
AN-553: Adjusting the Calibration Coefficients on the
AD771X Family of ADCs
AN-607: Selecting a Low Bandwidth (<15 kSPS) Sigma-
Delta ADC
AN-615: Peak-to-Peak Resolution Versus Effective
Resolution
Data Sheet
AD7714: CMOS, 3V/5V, 500 µA, 24-Bit Sigma-Delta, Signal
Conditioning ADC Data Sheet
User Guides
UG-761: Evaluation Board for the AD7714-3, 24-Bit Low
Power Sigma-Delta ADC
TOOLS AND SIMULATIONS
AD7714 Digital Filter Model
dt_Register_Assistant
Sigma-Delta ADC Tutorial
REFERENCE MATERIALS
Technical Articles
Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
MS-2210: Designing Power Supplies for High Speed ADC
Part 1: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
Part 2: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
DESIGN RESOURCES
AD7714 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD7714 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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Parameter A Versions
1
Units Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 24 Bits min Guaranteed by Design. Bipolar Mode. For Filter Notches 60 Hz
22 Bits min For Filter Notch = 100 Hz
18 Bits min For Filter Notch = 250 Hz
15 Bits min For Filter Notch = 500 Hz
12 Bits min For Filter Notch = 1 kHz
Output Noise See Tables I to IV Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity ±0.0015 % of FSR max Filter Notches 60 Hz
Unipolar Offset Error See Note 2
Unipolar Offset Drift
3
0.5 µV/°C typ For Gains of 1, 2, 4
0.3 µV/°C typ For Gains of 8, 16, 32, 64, 128
Bipolar Zero Error See Note 2
Bipolar Zero Drift
3
0.5 µV/°C typ For Gains of 1, 2, 4
0.3 µV/°C typ For Gains of 8, 16, 32, 64, 128
Positive Full-Scale Error
4
See Note 2
Full-Scale Drift
3, 5
0.5 µV/°C typ For Gains of 1, 2, 4
0.3 µV/°C typ For Gains of 8, 16, 32, 64, 128
Gain Error
6
See Note 2
Gain Drift
3, 7
0.5 ppm of FSR/°C typ
Bipolar Negative Full-Scale Error ±0.0015 % of FSR max Typically ±0.0004%
Bipolar Negative Full-Scale Drift
3
1 µV/°C typ For Gains of 1, 2, 4
0.6 µV/°C typ For Gains of 8, 16, 32, 64, 128
ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN Unless Noted
Input Common-Mode Rejection (CMR) 90 dB min At DC. Typically 102 dB
Normal-Mode 50 Hz Rejection
8
100 dB min For Filter Notches of 10
Hz
, 25
Hz
, 50 Hz, ±0.02 × f
NOTCH
Normal-Mode 60 Hz Rejection
8
100 dB min For Filter Notches of 10
Hz
, 30
Hz
, 60 Hz, ±0.02 × f
NOTCH
Common-Mode 50 Hz Rejection
8
150 dB min For Filter Notches of 10
Hz
, 25
Hz
, 50 Hz, ±0.02 × f
NOTCH
Common-Mode 60 Hz Rejection
8
150 dB min For Filter Notches of 10
Hz
, 30
Hz
, 60 Hz, ±0.02 × f
NOTCH
Common-Mode Voltage Range
9
AGND to AV
DD
V min to V max AIN for BUFFER = 0 and REF IN
Absolute AIN/REF IN Voltage
9
AGND – 30 mV V min AIN for BUFFER = 0 and REF IN
AV
DD
+ 30 mV V max
Absolute/Common-Mode AIN Voltage
9
AGND + 50 mV V min BUFFER = 1. A Version
AV
DD
– 1.5 V V max
AIN Input Current
8
1 nA max A Version
AIN Sampling Capacitance
8
7 pF max
AIN Differential Voltage Range
10
0 to +V
REF
/GAIN
11
nom Unipolar Input Range (B/U Bit of Filter High Register = 1)
±V
REF
/GAIN nom Bipolar Input Range (B/U Bit of Filter High Register = 0)
AIN Input Sampling Rate, f
S
GAIN × f
CLK␣ IN
/64 For Gains of 1, 2, 4
f
CLK␣ IN
/8 For Gains of 8, 16, 32, 64, 128
REF IN(+) – REF IN(–) Voltage +2.5 V nom ±1% for Specified Performance. Functional with Lower V
REF
REF IN Input Sampling Rate, f
S
f
CLK IN
/64
LOGIC INPUTS
Input Current ±10 µA max
All Inputs Except MCLK IN
V
INL
, Input Low Voltage 0.8 V max DV
DD
= +5 V
V
INL
, Input Low Voltage 0.4 V max DV
DD
= +3.3␣ V
V
INH
, Input High Voltage 2.4 V min DV
DD
= +5 V
V
INH
, Input High Voltage 2.0 V min DV
DD
= +3.3 V
MCLK IN Only
V
INL
, Input Low Voltage 0.8 V max DV
DD
= +5␣ V
V
INL
, Input Low Voltage 0.4 V max DV
DD
= +3.3␣ V
V
INH
, Input High Voltage 3.5 V min DV
DD
= +5␣ V
V
INH
, Input High Voltage 2.5 V min DV
DD
= +3.3␣ V
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 800␣ µA Except for MCLK OUT.
12
DV
DD
= +5 V
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 100␣ µA Except for MCLK OUT.
12
DV
DD
= +3.3 V
V
OH
, Output High Voltage 4.0 V min I
SOURCE
= 200 µA Except for MCLK OUT.
12
DV
DD
= +5␣ V
V
OH
, Output High Voltage DV
DD
– 0.6 V V min I
SOURCE
= 100 µA Except for MCLK OUT.
12
DV
DD
= +3.3␣ V
Floating State Leakage Current ±10 µA max
Floating State Output Capacitance
13
9 pF typ
Data Output Coding Binary Unipolar Mode
Offset Binary Bipolar Mode
NOTES
1
Temperature range is as follows: A Versions: –40°C to +85°C.
2
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.
3
Recalibration at any temperature will remove these drift errors.
4
Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
5
Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
6
Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for
bipolar ranges.
AD7714-5–SPECIFICATIONS
(AV
DD
= +5␣ V, DV
DD
= +3.3␣ V or +5␣ V, REF IN(+) = +2.5␣ V; REF␣ IN(–) = AGND;
f
CLK IN
= 2.4576␣ MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
REV. C
–2–

AD7714ARSZ-5REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 3V/5V 500uA 24B Signal Condition
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