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AD7714ARSZ-5REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
2
AD7714
REV. C
–9–
PIN FUNCTION DESCRIPTION
DIP/SOIC PIN NUMBERS
Pin
No. Mnemonic Function
1 SCLK Serial Clock. Logic Input. An external serial clock is applied to this input to access serial data from the
AD7714. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses.
Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7714 in smaller
batches of data.
2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can
be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified with clock
input frequencies of both 1 MHz and 2.4576 MHz.
3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK
IN and MCLK␣ OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock
signal. This clock can be used to provide a clock source for external circuits.
4 POL Clock Polarity. Logic Input. With this input low, the first transition of the serial clock in a data transfer
operation is from a low to a high. In microcontroller applications, this means that the serial clock should idle
low between data transfers. With this input high, the first transition of the serial clock in a data transfer
operation is from a high to a low. In microcontroller applications, this means that the serial clock should idle
high between data transfers.
5 SYNC Logic Input which allows for synchronization of the digital filters and analog modulators when using a number
of AD7714s. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration
control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the digital
interface and does not reset DRDY if it is low.
6 RESET Logic Input. Active low input which resets the control logic, interface logic, digital filter and analog modulator
of the part to power-on status.
7 AIN1 Analog Input Channel 1. Programmable-gain analog input which can be used as a pseudo-differential input
when used with AIN6 or as the positive input of a differential analog input pair when used with AIN2 (see
Communications Register section).
8 AIN2 Analog Input Channel 2. Programmable-gain analog input which can be used as a pseudo-differential input
when used with AIN6 or as the negative input of a differential analog input pair when used with AIN1 (see
Communications Register section).
9 AIN3 Analog Input Channel 3. Programmable-gain analog input which can be used as a pseudo-differential input
when used with AIN6 or as the positive input of a differential analog input pair when used with AIN4 (see
Communications Register section).
10 AIN4 Analog Input Channel 4. Programmable-gain analog input which can be used as a pseudo-differential input
when used with AIN6 or as the negative input of a differential analog input pair when used with AIN3 (see
Communications Register section).
11 STANDBY Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to
typically 5 µA.
12 AV
DD
Analog Positive Supply Voltage, A Grade Versions: +3.3␣ V nominal (AD7714-3) or +5␣ V nominal (AD7714-5);
Y Grade Versions: 3 V or 5 V nominal.
13 BUFFER Buffer Option Select. Logic Input. With this input low, the on-chip buffer on the analog input (after the
multiplexer and before the analog modulator) is shorted out. With the buffer shorted out the current flowing in
the AV
DD
line is reduced to 270 µA. With this input high, the on-chip buffer is in series with the analog input
allowing the inputs to handle higher source impedances.
14 REF IN(–) Reference Input. Negative input of the differential reference input to the AD7714. The REF IN(–) can lie
anywhere between AV
DD
and AGND provided REF␣ IN(+) is greater than REF IN(–).
15 REF IN(+) Reference Input. Positive input of the differential reference input to the AD7714. The reference input is
differential with the provision that REF IN(+) must be greater than REF IN(–). REF IN(+) can lie anywhere
between AV
DD
and AGND.
16 AIN5 Analog Input Channel 5. Programmable-gain analog input which is the positive input of a differential analog
input pair when used with AIN6 (see Communications Register section).
17 AIN6 Analog Input Channel 6. Reference point for AIN1 through AIN4 in pseudo-differential mode or as the
negative input of a differential input pair when used with AIN5 (see Communications Register section).
18 AGND Ground reference point for analog circuitry.
AD7714
REV. C–10–
PIN FUNCTION DESCRIPTION (Continued)
Pin
No. Mnemonic Function
19 CS Chip Select. Active low Logic Input used to select the AD7714. With this input hard-wired low, the AD7714
can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS
can be used to select the device in systems with more than one device on the serial bus or as a frame
synchronization signal in communicating with the AD7714.
20 DRDY Logic output. A logic low on this output indicates that a new output word is available from the AD7714 data
register. The DRDY pin will return high upon completion of a read operation of a full output word. If no data
read has taken place, after an output update, the DRDY line will return high for 500 × t
CLK␣ IN
cycles prior to
the next output update. This gives an indication of when a read operation should not be attempted to avoid
reading from the data register as it is being updated. DRDY is also used to indicate when the AD7714 has
completed its on-chip calibration sequence.
21 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output shift
register can contain information from the calibration registers, mode register, communications register, filter
selection registers or data register depending on the register selection bits of the Communications Register.
22 DIN Serial Data Input with serial data being written to the input shift register on the part. Data from this input shift
register is transferred to the calibration registers, mode register, communications register or filter selection
registers depending on the register selection bits of the Communications Register.
23 DV
DD
Digital Supply Voltage, A Grade Versions: +3.3␣ V or +5 V nominal; Y Grade Versions: 3 V or 5 V nominal.
24 DGND Ground reference point for digital circuitry.
BIPOLAR NEGATIVE FULL-SCALE ERROR
This is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – V
REF
/GAIN + 0.5␣ LSB) when operat-
ing in the bipolar mode.
POSITIVE FULL-SCALE OVERRANGE
Positive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages on AIN(+) input greater than
AIN(–) + V
REF
/GAIN (for example, noise peaks or excess volt-
ages due to system gain errors in system calibration routines)
without introducing errors due to overloading the analog modu-
lator or overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGE
This is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – V
REF
/GAIN without overloading the
analog modulator or overflowing the digital filter. Note that the
analog input will accept negative voltage peaks even in the uni-
polar mode provided that AIN(+) is greater than AIN(–) and
greater than AGND – 30␣ mV.
OFFSET CALIBRATION RANGE
In the system calibration modes, the AD7714 calibrates its
offset with respect to the analog input. The Offset Calibration
Range specification defines the range of voltages that the
AD7714 can accept and still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGE
This is the range of voltages that the AD7714 can accept in the
system calibration mode and still calibrate full scale correctly.
INPUT SPAN
In system calibration schemes, two voltages applied in sequence
to the AD7714’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full scale that the AD7714 can
accept and still calibrate gain accurately.
TERMINOLOGY*
INTEGRAL NONLINEARITY
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point
0.5 LSB above the last code transition (111 . . . 110 to
111 . . . 111). The error is expressed as a percentage of full
scale.
POSITIVE FULL-SCALE ERROR
Positive Full-Scale Error is the deviation of the last code transi-
tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage
(AIN(–) + V
REF
/GAIN – 3/2 LSBs). It applies to both unipolar
and bipolar analog input ranges.
UNIPOLAR OFFSET ERROR
Unipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
BIPOLAR ZERO ERROR
This is the deviation of the midscale transition (0111 . . . 111
to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) –
0.5 LSB) when operating in the bipolar mode.
GAIN ERROR
This is a measure of the span error of the ADC. It includes full-
scale errors but not zero-scale errors. For unipolar input ranges
it is defined as (full-scale error – unipolar offset error) while for
bipolar input ranges it is defined as (full-scale error – bipolar
zero error).
*AIN(–) refers to the negative input of the differential input pairs or to AIN6
when referring to the pseudo-differential input configurations.
2
AD7714
REV. C
–11–
AD7714-5 OUTPUT NOISE
Table Ia shows the output rms noise and effective resolution for some typical notch and –3␣ dB frequencies for the AD7714-5 with
f
CLK␣ IN
= 2.4576␣ MHz while Table Ib gives the information for f
CLK IN
= 1␣ MHz. The numbers given are for the bipolar input ranges
with a V
REF
of +2.5␣ V and with BUFFER = 0. These numbers are typical and are generated at an analog input voltage of 0␣ V. The
numbers in brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5␣ LSB). The effective resolu-
tion of the device is defined as the ratio of the output rms noise to the input full scale (i.e., 2 × V
REF
/GAIN). It should be noted that
it is not calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms numbers
while effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms noise as
quoted in the tables.
The output noise from the part comes from two sources. The first is the electrical noise in the semiconductor devices used in the
implementation of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quan-
tization noise is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at
an even lower level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter
notch settings (below 100␣ Hz approximately for f
CLK IN
= 2.4576␣ MHz and below 40␣ Hz approximately for f
CLK IN
= 1␣ MHz) tend to
be device noise dominated while higher notch settings are dominated by quantization noise. Changing the filter notch and cutoff
frequency in the quantization-noise dominated region results in a more dramatic improvement in noise performance than it does in
the device-noise dominated region as shown in Table I. Furthermore, quantization noise is added after the PGA, so effective resolu-
tion is largely independent of gain for the higher filter notch frequencies. Meanwhile, device noise is added in the PGA and, there-
fore, effective resolution reduces at high gains for lower notch frequencies. Additionally, in the device-noise dominated region, the
output noise (in µV) is largely independent of reference voltage while in the quantization-noise dominated region, the noise is pro-
portional to the value of the reference. It is possible to do post-filtering on the device to improve the output data rate for a given
–3␣ dB frequency and also to further reduce the output noise.
At the lower filter notch settings (below 60␣ Hz for f
CLK IN
= 2.4576␣ MHz and below 25␣ Hz for f
CLK IN
= 1␣ MHz), the no missing
codes performance of the device is at the 24-bit level. At the higher settings, more codes will be missed until at 1␣ kHz notch setting
for f
CLK␣ IN
= 2.4576␣ MHz (400␣ Hz for f
CLK IN
= 1␣ MHz), no missing codes performance is only guaranteed to the 12-bit level.
Table Ia. AD7714-5 Output Noise/Resolution vs. Gain and First Notch for f
CLK IN
= 2.4576␣ MHz, BUFFER = 0
Filter First
Typical Output RMS Noise in ␮V (Effective Resolution in Bits)
Notch & O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate Frequency 1 2 4 8 16 32 64 128
5␣ Hz 1.31␣ Hz 0.87 (22.5) 0.48 (22.5) 0.24 (22.5) 0.2 (21.5) 0.18 (20.5) 0.17 (20) 0.17 (19) 0.17 (18)
10␣ Hz 2.62␣ Hz 1.0 (22.5) 0.78 (21.5) 0.48 (21.5) 0.33 (21) 0.25 (20.5) 0.25 (19.5) 0.25 (18.5) 0.25 (17.5)
25␣ Hz 6.55␣ Hz 1.8 (21.5) 1.1 (21) 0.63 (21) 0.5 (20) 0.44 (19.5) 0.41 (18.5) 0.38 (17.5) 0.38 (16.5)
30␣ Hz 7.86␣ Hz 2.5 (21) 1.31 (21) 0.84 (20.5) 0.57 (20) 0.46 (19.5) 0.43 (18.5) 0.4 (17.5) 0.4 (16.5)
50␣ Hz 13.1␣ Hz 4.33 (20) 2.06 (20) 1.2 (20) 0.64 (20) 0.54 (19) 0.46 (18.5) 0.46 (17.5) 0.46 (16.5)
60␣ Hz 15.72␣ Hz 5.28 (20) 2.36 (20) 1.33 (20) 0.87 (19.5) 0.63 (19) 0.62 (18) 0.6 (17) 0.56 (16)
100␣ Hz 26.2␣ Hz 12.1 (18.5) 5.9 (18.5) 2.86 (19) 1.91 (18.5) 1.06 (18) 0.83 (17.5) 0.82 (16.5) 0.76 (15.5)
250␣ Hz 65.5␣ Hz 127 (15.5) 58 (15.5) 29 (15.5) 15.9 (15.5) 6.7 (15.5) 3.72 (15.5) 1.96 (15.5) 1.5 (14.5)
500␣ Hz 131␣ Hz 533 (13) 267 (13) 137 (13) 66 (13) 38 (13) 20 (13) 8.6 (13) 4.4 (13)
1␣ kHz 262␣ Hz 2,850 (11) 1,258 (11) 680 (11) 297 (11) 131 (11) 99 (10.5) 53 (10.5) 28 (10.5)
Table Ib. AD7714-5 Output Noise/Resolution vs. Gain and First Notch for f
CLK IN
= 1␣ MHz, BUFFER = 0
Filter First
Typical Output RMS Noise in ␮V (Effective Resolution in Bits)
Notch & O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate Frequency 1 2 4 8 16 32 64 128
2␣ Hz 0.52␣ Hz 0.75 (22.5) 0.56 (22) 0.31 (22) 0.19 (21.5) 0.17 (21) 0.14 (20) 0.14 (19) 0.14 (18)
4␣ Hz 1.05␣ Hz 1.04 (22) 0.88 (21.5) 0.45 (21.5) 0.28 (21) 0.21 (20.5) 0.21 (19.5) 0.21 (18.5) 0.21 (17.5)
10␣ Hz 2.62␣ Hz 1.66 (21.5) 1.01 (21.5) 0.77 (20.5) 0.41 (20.5) 0.37 (19.5) 0.35 (19) 0.35 (18) 0.35 (17)
25 Hz 6.55␣ Hz 5.2 (20) 2.06 (20) 1.4 (20) 0.86 (19.5) 0.63 (19) 0.61 (18) 0.59 (17) 0.59 (16)
30␣ Hz 7.86␣ Hz 7.1 (19.5) 3.28 (19.5) 1.42 (19.5) 1.07 (19) 0.78 (18.5) 0.64 (18) 0.61 (17) 0.61 (16)
50␣ Hz 13.1␣ Hz 19.4 (18) 9.11 (18) 4.2 (18) 2.45 (18) 1.56 (17.5) 1.1 (17) 0.82 (16.5) 0.8 (15.5)
60␣ Hz 15.72␣ Hz 25 (17.5) 16 (17.5) 6.5 (17.5) 2.9 (17.5) 1.93 (17.5) 1.4 (17) 1.1 (16) 0.98 (15.5)
100␣ Hz 26.2␣ Hz 102 (15.5) 58 (15.5) 25 (15.5) 13.5 (15.5) 5.7 (15.5) 3.9 (15.5) 2.1 (15) 1.3 (15)
200␣ Hz 52.4␣ Hz 637 (13) 259 (13) 130 (13) 76 (13) 33 (13) 16 (13) 11 (13) 6 (12.5)
400␣ Hz 104.8␣ Hz 2,830 (11) 1,430 (11) 720 (11) 334 (11) 220 (10.5) 94 (10.5) 54 (10.5) 25 (10.5)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

AD7714ARSZ-5REEL

Mfr. #:
Buy AD7714ARSZ-5REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 3V/5V 500uA 24B Signal Condition
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