AD7714
REV. C–12–
AD7714-3 OUTPUT NOISE
Table IIa shows the output rms noise and effective resolution for some typical notch and –3␣ dB frequencies for the AD7714-3 with
f
CLK␣ IN
= 2.4576␣ MHz while Table IIb gives the information for f
CLK IN
= 1␣ MHz. The numbers given are for the bipolar input
ranges with a V
REF
of +1.25␣ V and BUFFER = 0. These numbers are typical and are generated at an analog input voltage of 0␣ V.
The numbers in brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5␣ LSB). The effective
resolution of the device is defined as the ratio of the output rms noise to the input full scale (i.e., 2 × V
REF
/GAIN). It should be
noted that it is not calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms
numbers while effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms
noise as quoted in the tables.
The output noise from the part comes from two sources. The first is the electrical noise in the semiconductor devices used in the
implementation of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quan-
tization noise is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at
an even lower level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter
notch settings (below 100␣ Hz approximately for f
CLK IN
= 2.4576␣ MHz and below 40␣ Hz approximately for f
CLK IN
= 1␣ MHz) tend to
be device noise dominated while higher notch settings are dominated by quantization noise. Changing the filter notch and cutoff
frequency in the quantization noise dominated region results in a more dramatic improvement in noise performance than it does in
the device-noise dominated region as shown in Table II. Furthermore, quantization noise is added after the PGA, so effective reso-
lution is largely independent of gain for the higher filter notch frequencies. Meanwhile, device noise is added in the PGA and, there-
fore, effective resolution suffers a little at high gains for lower notch frequencies. Additionally, in the device-noise dominated region,
the output noise (in µV) is largely independent of reference voltage while in the quantization-noise dominated region, the noise is
proportional to the value of the reference. It is possible to do post-filtering on the device to improve the output data rate for a given
–3␣ dB frequency and also to further reduce the output noise.
At the lower filter notch settings (below 60␣ Hz for f
CLK IN
= 2.4576␣ MHz and below 25␣ Hz for f
CLK IN
= 1␣ MHz), the no missing
codes performance of the device is at the 24-bit level. At the higher settings, more codes will be missed until at 1␣ kHz notch setting
for f
CLK␣ IN
= 2.4576␣ MHz (400␣ Hz for f
CLK IN
= 1␣ MHz), no missing codes performance is only guaranteed to the 12-bit level.
Filter First
Typical Output RMS Noise in V (Effective Resolution in Bits)
Notch & O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate Frequency 1 2 4 8 16 32 64 128
2␣ Hz 0.52␣ Hz 0.86 (21.5) 0.58 (21) 0.32 (21) 0.21 (20.5) 0.2 (19.5) 0.2 (18.5) 0.2 (17.5) 0.2 (16.5)
4␣ Hz 1.05␣ Hz 1.26 (21) 0.74 (20.5) 0.44 (20.5) 0.35 (20) 0.3 (19) 0.3 (18) 0.3 (17) 0.3 (16)
10␣ Hz 2.62␣ Hz 1.68 (20.5) 1.33 (20) 0.73 (20) 0.5 (19) 0.49 (18.5) 0.49 (17.5) 0.48 (16.5) 0.47 (15.5)
25␣ Hz 6.55␣ Hz 3.82 (19.5) 2.0 (19.5) 1.2 (19) 0.88 (18.5) 0.66 (18) 0.57 (17) 0.55 (16) 0.55 (15)
30␣ Hz 7.86␣ Hz 4.88 (19) 2.1 (19) 1.3 (19) 0.93 (18.5) 0.82 (17.5) 0.69 (17) 0.68 (16) 0.66 (15)
50␣ Hz 13.1␣ Hz 11 (18) 4.8 (18) 2.4 (18) 1.4 (18) 1.4 (17) 0.73 (16.5) 0.71 (15.5) 0.7 (15)
60␣ Hz 15.72␣ Hz 14.7 (17.5) 7.5 (17.5) 3.8 (17.5) 2.6 (17) 1.5 (16.5) 0.95 (16.5) 0.88 (15) 0.9 (14.5)
100␣ Hz 26.2␣ Hz 61 (15.5) 30 (15.5) 12 (15.5) 6.1 (15.5) 2.9 (15.5) 2.4 (15) 1.8 (14.5) 1.8 (13.5)
200␣ Hz 52.4␣ Hz 275 (13) 130 (13) 65 (13) 33 (13) 17 (13) 11 (13) 6.3 (12.5) 3 (12.5)
400 Hz 104.8␣ Hz 1435 (11) 720 (11) 362 (11) 175 (11) 110 (10.5) 51 (10.5) 31 (10.5) 12 (10.5)
Table IIa. AD7714-3 Output Noise/Resolution vs. Gain and First Notch for f
CLK IN
= 2.4576␣ MHz, BUFFER = 0
Filter First
Typical Output RMS Noise in V (Effective Resolution in Bits)
Notch & O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate Frequency 1 2 4 8 16 32 64 128
5␣ Hz 1.31␣ Hz 1.07 (21) 0.68 (21) 0.29 (21) 0.24 (20) 0.22 (19.5) 0.22 (18.5) 0.22 (17.5) 0.22 (16.5)
10␣ Hz 2.62␣ Hz 1.69 (20.5) 1.1 (20) 0.56 (20) 0.35 (19.5) 0.33 (19) 0.33 (18) 0.33 (17) 0.33 (16)
25␣ Hz 6.55␣ Hz 3.03 (19.5) 1.7 (19.5) 0.89 (19.5) 0.55 (19) 0.49 (18.5) 0.46 (17.5) 0.46 (16.5) 0.45 (15.5)
30␣ Hz 7.86␣ Hz 3.55 (19.5) 2.1 (19) 1.1 (19) 0.61 (18.5) 0.58 (18) 0.57 (17) 0.55 (16) 0.55 (15)
50␣ Hz 13.1␣ Hz 4.72 (19) 2.3 (19) 1.5 (18.5) 0.84 (18.5) 0.7 (18) 0.68 (17) 0.67 (16) 0.66 (15)
60␣ Hz 15.72␣ Hz 5.12 (19) 3.1 (18.5) 1.6 (18) 0.98 (18) 0.9 (17.5) 0.7 (17) 0.69 (16) 0.68 (15)
100␣ Hz 26.2␣ Hz 9.68 (18) 5.6 (18) 2.4 (18) 1.3 (18) 1.1 (17) 0.95 (16.5) 0.88 (15.5) 0.9 (14.5)
250␣ Hz 65.5␣ Hz 44 (16) 31 (15.5) 15 (15.5) 5.8 (15.5) 3.7 (15.5) 2.4 (15) 1.8 (14.5) 1.8 (13.5)
500␣ Hz 131␣ Hz 304 (13) 129 (13) 76 (13) 33 (13) 20 (13) 11 (13) 6.3 (12.5) 3 (12.5)
1␣ kHz 262␣ Hz 1410 (11) 715 (11) 350 (11) 177 (11) 101 (10.5) 51 (10.5) 31 (10.5) 12 (10.5)
Table IIb. AD7714-3 Output Noise/Resolution vs. Gain and First Notch for f
CLK IN
= 1␣ MHz, BUFFER = 0
2
AD7714
REV. C
–13–
BUFFERED MODE NOISE
Table III shows the typical output rms noise and effective resolution for some typical notch and –3␣ dB frequencies for the AD7714-
5 with f
CLK␣ IN
= 2.4576␣ MHz and BUFFER = +5 V. Table IV gives the information for the AD7714-3 again with f
CLK IN
= 2.4576
MHz and BUFFER = +5␣ V. The numbers given are for the bipolar input ranges and are generated with a differential analog input
voltage of 0␣ V. For the AD7714-5, the V
REF
voltage is +2.5␣ V while for the AD7714 the V
REF
voltage is +1.25␣ V. The numbers in
brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5 LSB). The effective resolution of the
device is defined as the ratio of the output rms noise to the input full scale (i.e., 2 × V
REF
/GAIN). It should be noted that it is not
calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms numbers while
effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms noise as quoted
in the tables.
Table III. AD7714-5 Buffered Mode Output Noise/Resolution for f
CLK IN
= 2.4576␣ MHz
Filter First
Typical Output RMS Noise in V (Effective Resolution in Bits)
Notch & O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate Frequency 1 2 4 8 16 32 64 128
5␣ Hz 1.31␣ Hz 0.99 (22.5) 0.68 (22) 0.46 (21.5) 0.26 (21) 0.26 (20) 0.26 (19) 0.26 (18) 0.26 (17)
10␣ Hz 2.62␣ Hz 1.5 (21.5) 0.95 (21.5) 0.63 (21) 0.41 (20.5) 0.39 (19.5) 0.36 (18.5) 0.36 (17.5) 0.36 (16.5)
25␣ Hz 6.55␣ Hz 2.5 (21) 1.7 (20.5) 0.88 (20.5) 0.75 (19.5) 0.57 (19) 0.57 (18) 0.57 (17) 0.56 (16)
30␣ Hz 7.86␣ Hz 2.9 (20.5) 1.8 (20.5) 1 (20) 0.87 (19.5) 0.75 (18.5) 0.72 (17.5) 0.72 (16.5) 0.71 (15.5)
50␣ Hz 13.1␣ Hz 4.2 (20) 2.5 (20) 1.5 (19.5) 1.1 (19) 0.94 (18.5) 0.94 (17.5) 0.94 (16.5) 0.87 (15.5)
60␣ Hz 15.72␣ Hz 6.1 (19.5) 2.9 (19.5) 2 (19.5) 1.2 (19) 1 (18.5) 0.97 (17.5) 0.95 (16.5) 0.94 (15.5)
100␣ Hz 26.2␣ Hz 13.8 (18.5) 6.5 (18.5) 3.5 (18.5) 2.2 (18) 1.3 (18) 1.2 (17) 1.3 (16) 1.1 (15)
250␣ Hz 65.5␣ Hz 87 (16) 56 (15.5) 25 (15.5) 11 (15.5) 5.7 (15.5) 3.6 (15.5) 2.4 (15) 2.1 (14)
500␣ Hz 131␣ Hz 508 (13.5) 241 (13.5) 117 (13.5) 73 (13) 34 (13) 16 (13) 8.5 (13) 5.2 (13)
1␣ kHz 262␣ Hz 2860 (11) 1700 (10.5) 745 (10.5) 480 (10.5) 197 (10.5) 94 (10.5) 53 (10.5) 23 (10.5)
Table IV. AD7714-3 Buffered Mode Output Noise/Resolution for f
CLK IN
= 2.4576␣ MHz
Filter First
Typical Output RMS Noise in V (Effective Resolution in Bits)
Notch & O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate Frequency 1 2 4 8 16 32 64 128
5␣ Hz 1.31␣ Hz 1.16 (21) 0.76 (20.5) 0.34 (20) 0.29 (20) 0.29 (19) 0.28 (18) 0.26 (17) 0.26 (16)
10␣ Hz 2.62␣ Hz 1.7 (20.5) 1 (20.5) 0.7 (20) 0.46 (19.5) 0.45 (18.5) 0.4 (17.5) 0.4 (16.5) 0.4 (15.5)
25␣ Hz 6.55␣ Hz 3.5 (19.5) 1.8 (19.5) 1.1 (19) 0.74 (18.5) 0.63 (18) 0.6 (17) 0.6 (16) 0.6 (15)
30␣ Hz 7.86␣ Hz 3.7 (19.5) 2.2 (19) 1.3 (19) 0.76 (18.5) 0.68 (18) 0.66 (17) 0.66 (16) 0.66 (15)
50␣ Hz 13.1␣ Hz 4.5 (19) 3 (18.5) 1.7 (18.5) 1.0 (18) 0.92 (17.5) 0.9 (16.5) 0.89 (15.5) 0.89 (14.5)
60␣ Hz 15.72␣ Hz 5.3 (19) 3.3 (18.5) 1.8 (18.5) 1.1 (18) 1 (17) 0.96 (16.5) 0.96 (15.5) 0.96 (14.5)
100␣ Hz 26.2␣ Hz 10 (18) 4.9 (18) 3.1 (17.5) 1.5 (17.5) 1.2 (17) 1.2 (16) 1.2 (15) 1.2 (14)
250␣ Hz 65.5␣ Hz 47 (15.5) 29 (15.5) 15 (15.5) 7.5 (15.5) 4.7 (15) 2.6 (15) 2.5 (14) 1.6 (13.5)
500␣ Hz 131␣ Hz 300 (13.5) 171 (13) 74 (13) 35 (13) 21 (13) 8.6 (13) 5.6 (13) 3.1 (12.5)
1␣ kHz 262␣ Hz 1722 (10.5) 735 (10.5) 380 (10.5) 230 (10.5) 93 (10.5) 55 (10.5) 30 (10.5) 12 (10.5)
AD7714
REV. C–14–
ON-CHIP REGISTERS
The AD7714 contains eight on-chip registers which can be accessed via the serial port of the part. The first of these is a Communica-
tions Register which controls the channel selection, decides whether the next operation is a read or write operation and also decides
which register the next read or write operation accesses. All communications to the part must start with a write operation to the
Communications Register. After power-on or RESET, the device expects a write to its Communications Register. The data written
to this register determines whether the next operation to the part is a read or a write operation and also determines to which register
this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the
Communications Register followed by a write to the selected register. A read operation from any other register on the part (including
the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected
register. The communications register also controls channel selection and the DRDY status is also available by reading from the
Communications Register. The second register is a Mode Register which determines calibration mode and gain setting. The third
register is labelled the Filter High Register and this determines the word length, bipolar/unipolar operation and contains the upper 4
bits of the filter selection word. The fourth register is labelled the Filter Low Register and contains the lower 8 bits of the filter selec-
tion word. The fifth register is a Test Register which is accessed when testing the device. The sixth register is the Data Register from
which the output data from the part is accessed. The final registers allow access to the part’s calibration registers. The Zero Scale
Calibration Register allows access to the zero scale calibration coefficients for the selected input channel while the Full Scale Calibra-
tion Register allows access to the full scale calibration coefficients for the selected input channel. The registers are discussed in more
detail in the following sections.
Communications Register (RS2-RS0 = 0, 0, 0)
The Communications Register is an 8-bit register from which data can either be read or to which data can be written. All communi-
cations to the part must start with a write operation to the Communications Register. The data written to the Communications Reg-
ister determines whether the next operation is a read or write operation and to which register this operation takes place. Once the
subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to
the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7714 is in this
default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, if a
write operation of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7714 returns to
this default state. Table V outlines the bit designations for the Communications Register.
Table V. Communications Register
Table VI. Register Selection
0/DRDY RS2 RS1 RS0 R/W CH2 CH1 CH0
0/DRDY For a write operation, a 0 must be written to this bit so that the write operation to the Communications Register
actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next 7 bits will be loaded to the
Communications Register. For a read operation, this bit provides the status of the DRDY flag from the part. The
status of this bit is the same as the DRDY output pin.
RS2–RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select to which one of eight on-chip
registers the next read or write operation takes place as shown in Table VI along with the register size.
RS2 RS1 RS0 Register Register Size
0 0 0 Communications Register 8 Bits
0 0 1 Mode Register 8 Bits
0 1 0 Filter High Register 8 Bits
0 1 1 Filter Low Register 8 Bits
1 0 0 Test Register 8 Bits
1 0 1 Data Register 16 Bits or 24 Bits
1 1 0 Zero-Scale Calibration Register 24 Bits
1 1 1 Full-Scale Calibration Register 24 Bits

AD7714ARSZ-5REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 3V/5V 500uA 24B Signal Condition
Lifecycle:
New from this manufacturer.
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