Parameter Y Versions Units Conditions/Comments
LOGIC OUTPUTS (Continued))
V
OH
, Output High Voltage DV
DD
– 0.6 V min I
SOURCE
= 100 µA with DV
DD
= 3 V. Except for MCLK OUT
12
Floating State Leakage Current ±10 µA max
Floating State Output Capacitance
13
9 pF typ
D
ata Output Coding Binary Unipolar Mode
Offset Binary Bipolar Mode
TRANSDUCER BURNOUT
14
Current 1 µA nom
Initial Tolerance ±10 % typ
Drift 0.1 %/°C typ
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
15
(1.05 × V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Negative Full-Scale Calibration Limit
15
–(1.05 × V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Offset Calibration Limit
16
–(1.05 × V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Input Span
16
0.8 × V
REF
/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)
(2.1 × V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage +2.7 to +3.3 or V
+4.75 to +5.25 V For Specified Performance
DV
DD
Voltage +2.7 to +5.25 V For Specified Performance
Power Supply Currents
AV
DD
Current AV
DD
= 3 V or 5␣ V. BST Bit of Filter High Register = 0
17
, CLKDIS = 1
0.28 mA max Typically 0.22 mA. BUFFER = 0 V. f
CLK IN
= 1␣ MHz or 2.4576␣ MHz
0.6 mA max Typically 0.45 mA. BUFFER = DV
DD
. f
CLK IN
= 1␣ MHz or 2.4576␣ MHz
AV
DD
= 3 V or 5␣ V. BST Bit of Filter High Register = 1
17
0.5 mA max Typically 0.38␣ mA. BUFFER = 0␣ V. f
CLK IN
= 2.4576␣ MHz
1.1 mA max Typically 0.8␣ mA. BUFFER = DV
DD
. f
CLK IN
= 2.4576␣ MHz
DV
DD
Current
18
Digital I/Ps = 0␣ V or DV
DD.
External MCLK IN, CLKDIS = 1
0.080 mA max Typically 0.06␣ mA. DV
DD
= 3 V. f
CLK IN
= 1␣ MHz
0.16 mA max Typically 0.13␣ mA. DV
DD
= 5␣ V. f
CLK IN
= 1␣ MHz
0.18 mA max Typically 0.15␣ mA. DV
DD
= 3 V. f
CLK IN
= 2.4576␣ MHz
0.35 mA max Typically 0.3 mA. DV
DD
= 5␣ V. f
CLK IN
= 2.4576␣ MHz
Power Supply Rejection
19
See Note 20 dB typ
Normal-Mode Power Dissipation
18
AV
DD
= DV
DD
= +3 V. Digital I/Ps = 0␣ V or DV
DD
. External MCLK IN
BST Bit of Filter High Register = 0
17
1.05 mW max Typically 0.84␣ mW. BUFFER = 0␣ V. f
CLK IN
= 1␣ MHz. BST Bit = 0
2.04 mW max Typically 1.53␣ mW. BUFFER = +3 V. f
CLK IN
= 1␣ MHz. BST Bit = 0
1.35 mW max Typically 1.11␣ mW. BUFFER = 0␣ V. f
CLK IN
= 2.4576␣ MHz. BST Bit = 0
2.34 mW max Typically 1.9␣ mW. BUFFER = +3 V. f
CLK IN
= 2.4576␣ MHz. BST Bit = 0
Normal-Mode Power Dissipation AV
DD
= DV
DD
= +5␣ V. Digital I/Ps = 0␣ V or DV
DD
. External MCLK IN
2.1 mW max Typically 1.75 mW. BUFFER = 0␣ V. f
CLK IN
= 1␣ MHz. BST Bit = 0
3.75 mW max Typically 2.9 mW. BUFFER = +5␣ V. f
CLK IN
= 1␣ MHz. BST Bit = 0
3.1 mW max Typically 2.6␣ mW. BUFFER = 0␣ V. f
CLK IN
= 2.4576␣ MHz. BST Bit = 0
4.75 mW max Typically 3.75␣ mW. BUFFER = +5␣ V. f
CLK IN
= 2.4576␣ MHz. BST Bit = 0
Standby (Power-Down) Current
21
18 µA max External MCLK IN = 0 V or DV
DD
. Typically 9␣ µA. V
DD
= +5 V
Standby (Power-Down) Current
21
10 µA max External MCLK IN = 0 V or DV
DD
. Typically 4␣ µA. V
DD
= +3 V
NOTES
1
Temperature range is as follows: Y Version: –40°C to +105°C.
2
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.
3
Recalibration at any temperature will remove these drift errors.
4
Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
5
Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
6
Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for
bipolar ranges.
7
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with background calibration.
8
These numbers are guaranteed by design and/or characterization.
9
The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
10
The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII for which
inputs form differential pairs.
11
V
REF
= REF IN(+) – REF IN(–).
12
These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
13
Sample tested at +25°C to ensure compliance.
14
See Burnout Current section.
15
After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.
16
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30␣ mV or go more negative than AGND␣ –␣ 30␣ mV. The offset calibration
limit applies to both the unipolar zero point and the bipolar zero point.
17
For higher gains (≥8) at f
CLK␣ IN
= 2.4576␣ MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.
18
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
DD
current and power dissipation will vary depending on the crystal or resonator
type (see Clocking and Oscillator Circuit section).
19
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter
notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.
20
PSRR depends on gain.
Gain 1 2 4 8–128
AV
DD
= 3 V 86 dB 78 dB 85 dB 93 dB
AV
DD
= 5 V 90 dB 78 dB 84 dB 91 dB
21
If the external master clock continues to run in standby mode, the standby current increases to 150 µA typical with 5 V supplies and 75 µA typical with 3.3 V supplies. When using a crystal
or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or
resonator type (see Standby Mode section).
Specifications subject to change without notice.
AD7714Y
REV. C
–6–
