AD7714ARSZ-5REEL Datasheet AD7714ARZ-5, AD7714YRZ, AD7714YRUZ | P25-P27

AD7714

REV. C–24–

The part also offers ZS Self-Calibration and FS Self-Calibration

options. In these cases, the part performs just a zero-scale or

full-scale calibration respectively and not a full calibration of the

part. A full-scale calibration should not be carried out unless

the part contains valid zero-scale coefficients. These calibrations

are initiated on the AD7714 by writing the appropriate values

(1, 1, 0 for ZS Self-Calibration and 1, 1, 1 for FS Self Calibra-

tion) to the MD2, MD1 and MD0 bits of the Mode Register.

The zero-scale or full-scale calibration is exactly the same as

that described for the full self-calibration. In these cases, the

duration of the calibration is 3 × 1/Output Rate. At this time the

MD2, MD1 and MD0 bits in the Mode Register return to

0, 0, 0. This gives the earliest indication that the calibration

sequence is complete. The DRDY line goes high when calibra-

tion is initiated and does not return low until there is a valid

new word in the data register. The time from the calibration

command being issued to DRDY going low is 6 × 1/Output

Rate. This is made up of 3 × 1/Output Rate for the zero-scale or

full-scale calibration and 3 × 1/Output Rate for a conversion on

the analog input. If DRDY is low before (or goes low during)

the calibration command write to the Mode Register, it may

take up to one modulator cycle (MCLK␣ IN/128) before DRDY

goes high to indicate that calibration is in progress. Therefore,

DRDY should be ignored for up to one modulator cycle after

the last bit of the calibration command is written to the Mode

The fact that the self-calibration can be performed as a two step

calibration offers another feature. After the sequence of a full

self calibration has been completed, additional offset or gain

calibrations can be performed by themselves to adjust the part’s

zero point or gain. Calibrating one of the parameters, either

offset or gain, will not affect the other parameter.

System Calibration

System calibration allows the AD7714 to compensate for system

gain and offset errors as well as its own internal errors. System

calibration performs the same slope factor calculations as self-

calibration but uses voltage values presented by the system to

the AIN inputs for the zero- and full-scale points. Full System

calibration requires a two-step process, a ZS System Calibration

followed by a FS System Calibration.

For a full system calibration, the zero-scale point must be pre-

sented to the converter first. It must be applied to the converter

before the calibration step is initiated and remain stable until the

step is complete. Once the system zero scale has been set up at

the analog input, a ZS System Calibration is then initiated by

writing the appropriate values (0, 1, 0) to the MD2, MD1 and

MD0 bits of the Mode Register. The zero-scale system calibra-

tion is performed at the selected gain. The duration of the cali-

bration is 3 × 1/Output Rate. At this time, the MD2, MD1 and

MD0 bits in the Mode Register return to 0, 0, 0. This gives the

earliest indication that the calibration sequence is complete. The

DRDY line goes high when calibration is initiated and does not

return low until there is a valid new word in the data register.

The time from the calibration command being issued to DRDY

going low is 4 × 1/Output Rate. This is made up of 3 × 1/Output

Rate for the zero-scale system calibration and 1/Output Rate for

a conversion on the analog input. This conversion on the analog

input is on the same voltage as the zero-scale system calibration

and, therefore, the resultant word in the data register from this

conversion should be a zero-scale reading. If DRDY is low

before (or goes low during) the calibration command write to

the Mode Register, it may take up to one modulator cycle

(MCLK␣ IN/128) before DRDY goes high to indicate that cali-

bration is in progress. Therefore, DRDY should be ignored for

up to one modulator cycle after the last bit of the calibration

command is written to the Mode Register.

After the zero-scale point is calibrated, the full-scale point is

applied to AIN and the second step of the calibration process is

initiated by again writing the appropriate values (0, 1, 1) to

MD2, MD1 and MD0. Again the full-scale voltage must be set

up before the calibration is initiated, and it must remain stable

throughout the calibration step. The full-scale system calibra-

tion is performed at the selected gain. The duration of the cali-

bration is 3 × 1/Output Rate. At this time, the MD2, MD1 and

MD0 bits in the Mode Register return to 0, 0, 0. This gives the

earliest indication that the calibration sequence is complete. The

DRDY line goes high when calibration is initiated and does not

return low until there is a valid new word in the data register.

The time from the calibration command being issued to DRDY

going low is 4 × 1/Output Rate. This is made up of 3 × 1/Out-

put Rate for the full-scale system calibration and 1/Output Rate

for a conversion on the analog input. This conversion on the

analog input is on the same voltage as the full-scale system

calibration and, therefore, the resultant word in the data register

from this conversion should be a full-scale reading. If DRDY is

low before (or goes low during) the calibration command write

to the Mode Register, it may take up to one modulator cycle

(MCLK␣ IN/128) before DRDY goes high to indicate that cali-

bration is in progress. Therefore, DRDY should be ignored for

up to one modulator cycle after the last bit of the calibration

command is written to the Mode Register.

In the unipolar mode, the system calibration is performed

between the two endpoints of the transfer function; in the bipo-

lar mode, it is performed between midscale (zero differential

voltage) and positive full scale.

The fact that the system calibration is a two step calibration

offers another feature. After the sequence of a full system cali-

bration has been completed, additional offset or gain calibra-

tions can be performed by themselves to adjust the system zero

reference point or the system gain. Calibrating one of the

parameters, either system offset or system gain, will not affect

the other parameter. A full-scale calibration should not be car-

ried out unless the part contains valid zero-scale coefficients.

System calibration can also be used to remove any errors from

source impedances on the analog input when the part is used in

unbuffered mode. A simple R, C antialiasing filter on the front

end may introduce a gain error on the analog input voltage but

the system calibration can be used to remove this error.

AD7714

REV. C

–25–

System-Offset Calibration

System-offset calibration is a variation of both the system cali-

bration and self-calibration. In this case, the zero-scale point is

determined in exactly the same way as a ZS System Calibration.

The system zero-scale point is presented to the AIN inputs of

the converter. This must be applied to the converter before

the calibration step is initiated and remain stable until the step

is complete. Once the system zero scale has been set up, a

System-Offset Calibration is then initiated by writing the appro-

priate values (1, 0, 0) to the MD2, MD1 and MD0 bits of the

Mode Register. The zero-scale system calibration is performed

at the selected gain.

The full-scale calibration is performed in exactly the same way

as an FS Self Calibration. The full-scale calibration conversion

is performed at the selected gain on an internally generated

voltage of V

REF

/Selected Gain. This is a one step calibration

sequence and the time for calibration is 6 × 1/Output Rate. At

this time, the MD2, MD1 and MD0 bits in the Mode Register

return to 0, 0, 0. This gives the earliest indication that the cali-

bration sequence is complete. The DRDY line goes high when

calibration is initiated and does not return low until there is a

valid new word in the data register. The duration time from the

calibration command being issued to DRDY going low is 9 × 1/

Output Rate. This is made up of 3 × 1/Output Rate for the zero-

scale system calibration, 3 × 1/Output Rate for the full-scale

self-calibration and 3 × 1/Output Rate for a conversion on the

analog input. This conversion on the analog input is on the

same voltage as the zero-scale system calibration and, therefore,

the resultant word in the data register from this conversion

should be a zero-scale reading. If DRDY is low before (or goes

low during) the calibration command write to the Mode Regis-

ter, it may take up to one modulator cycle (MCLK␣ IN/128)

before DRDY goes high to indicate that calibration is in

progress. Therefore, DRDY should be ignored for up to one

modulator cycle after the last bit of the calibration command is

written to the Mode Register.

In the unipolar mode, the system-offset calibration is performed

between the two endpoints of the transfer function; in the bipolar

mode, it is performed between midscale and positive full scale.

Background Calibration

The AD7714 also offers a background calibration mode where

the part interleaves its calibration procedure with its normal

conversion sequence. In the background calibration mode, the

part provides continuous zero-scale self-calibrations; it does not

provide any full-scale calibrations. The zero-scale point used in

determining the calibration coefficients in this mode is exactly

the same as for a ZS Self-Calibration. The background calibra-

tion mode is invoked by writing 1, 0, 1 to the MD2, MD1,

MD0 bits of the Mode Register. When invoked, the back-

ground calibration mode performs a zero-scale self calibration

after every output update and this reduces the output data rate

of the AD7714 by a factor of six. Its advantage is that the part

is continually performing offset calibrations and automatically

updating its zero-scale calibration coefficients. As a result, the

effects of temperature drift, supply sensitivity and time drift on

zero-scale errors are automatically removed. When the back-

ground calibration mode is turned on, the part will remain in

this mode until bits MD2, MD1 and MD0 of the Mode Regis-

ter are changed.

Because the background calibration does not perform full-scale

calibrations, a self-calibration should be performed before plac-

ing the part in background calibration mode. Removal of the

offset drift in this mode leaves gain drift as the only source of

error not removed from the part. The typical gain drift of the

AD7714 with temperature is 0.2␣ ppm/°C. The SYNC input or

FSYNC bit should not be exercised when the part is in back-

ground calibration mode.

Span and Offset Limits

Whenever a system calibration mode is used, there are limits on

the amount of offset and span which can be accommodated.

The overriding requirement in determining the amount of offset

and gain which can be accommodated by the part is the require-

ment that the positive full-scale calibration limit is ≤ 1.05 ×

REF

/GAIN. This allows the input range to go 5% above the

nominal range. The built-in headroom in the AD7714’s analog

modulator ensures that the part will still operate correctly with a

positive full-scale voltage which is 5% beyond the nominal.

The range of input span in both the unipolar and bipolar modes

has a minimum value of 0.8 × V

REF

/GAIN and a maximum

value of 2.1 × V

REF

/GAIN. However, the span (which is the

difference between the bottom of the AD7714’s input range and

the top of its input range) has to take into account the limitation

on the positive full-scale voltage. The amount of offset which

can be accommodated depends on whether the unipolar or

bipolar mode is being used. Once again, the offset has to take

into account the limitation on the positive full-scale voltage. In

unipolar mode, there is considerable flexibility in handling nega-

tive (with respect to AIN(–)) offsets. In both unipolar and bipo-

lar modes, the range of positive offsets which can be handled by

the part depends on the selected span. Therefore, in determin-

ing the limits for system zero-scale and full-scale calibrations,

the user has to ensure that the offset range plus the span range

does exceed 1.05 × V

REF

/GAIN. This is best illustrated by

looking at a few examples.

If the part is used in unipolar mode with a required span of

0.8 × V

REF

/GAIN, the offset range the system calibration can

handle is from –1.05 × V

REF

/GAIN to +0.25 × V

REF

/GAIN. If

the part is used in unipolar mode with a required span of V

REF

GAIN, the offset range the system calibration can handle is

from –1.05 × V

REF

/GAIN to +0.05 × V

REF

/GAIN. Similarly, if

the part is used in unipolar mode and required to remove an

offset of 0.2 × V

REF

/GAIN, the span range the system calibra-

tion can handle is 0.85 × V

REF

/GAIN.

If the part is used in bipolar mode with a required span of

±0.4 × V

REF

/GAIN, then the offset range which the system cali-

bration can handle is from –0.65 × V

REF

/GAIN to +0.65 ×

REF

/GAIN. If the part is used in bipolar mode with a required

span of ±V

REF

/GAIN, the offset range the system calibration can

handle is from –0.05 × V

REF

/GAIN to +0.05 × V

REF

/GAIN.

Similarly, if the part is used in bipolar mode and required to

remove an offset of ±0.2 × V

REF

/GAIN, the span range the sys-

tem calibration can handle is ±0.85 × V

REF

/GAIN.

AD7714

REV. C–26–

Power-Up and Calibration

On power-up, the AD7714 performs an internal reset which sets

the contents of the internal registers to a known state. There

are default values loaded to all registers after a power-on or

reset. The default values contain nominal calibration coefficients

for the calibration registers. However, to ensure correct calibra-

tion for the device a calibration routine should be performed

after power-up.

The power dissipation and temperature drift of the AD7714 are

low and no warm-up time is required before the initial calibra-

tion is performed. However, if an external reference is being

used, this reference must have stabilized before calibration is

initiated. Similarly, if the clock source for the part is generated

from a crystal or resonator across the MCLK pins, the start-up

time for the oscillator circuit should elapse before a calibration

is initiated on the part (see below).

USING THE AD7714

Clocking and Oscillator Circuit

The AD7714 requires a master clock input, which may be an

external CMOS compatible clock signal applied to the MCLK␣ IN

pin with the MCLK␣ OUT pin left unconnected. Alternatively, a

crystal or ceramic resonator of the correct frequency can be

connected between MCLK␣ IN and MCLK␣ OUT in which case

the clock circuit will function as an oscillator, providing the

clock source for the part. The input sampling frequency, the

modulator sampling frequency, the –3␣ dB frequency, output

update rate and calibration time are all directly related to the

master clock frequency, f

CLK␣ IN

. Reducing the master clock

frequency by a factor of 2 will halve the above frequencies and

update rate and double the calibration time. The current drawn

from the DV

power supply is also directly related to f

CLK␣ IN

Reducing f

CLK␣ IN

by a factor of 2 will halve the DV

current

but will not affect the current drawn from the AV

power supply.

Using the part with a crystal or ceramic resonator between the

MCLK IN and MCLK OUT pins generally causes more cur-

rent to be drawn from DV

than when the part is clocked from

a driven clock signal at the MCLK IN pin. This is because the

on-chip oscillator circuit is active in the case of the crystal or

ceramic resonator. Therefore, the lowest possible current on

the AD7714 is achieved with an externally applied clock at the

MCLK IN pin with MCLK OUT unconnected and unloaded.

The amount of additional current taken by the oscillator

depends on a number of factors—first, the larger the value of

capacitor placed on the MCLK␣ IN and MCLK␣ OUT pins, then

the larger the DV

current consumption on the AD7714. Care

should be taken not to exceed the capacitor values recommended

by the crystal and ceramic resonator manufacturers to avoid

consuming unnecessary DV

current. Typical values recom-

mended by crystal or ceramic resonator manufacturers are in the

range of 30␣ pF to 50␣ pF and if the capacitor values on MCLK

IN and MCLK OUT are kept in this range they will not result

in any excessive DV

current. Another factor that influences

the DV

current is the effective series resistance (ESR) of the

crystal which appears between the MCLK IN and MCLK OUT

pins of the AD7714. As a general rule, the lower the ESR value

then the lower the current taken by the oscillator circuit.

When operating with a clock frequency of 2.4576␣ MHz, there is

no appreciable difference in the DV

current between an

externally applied clock and a crystal resonator when operating

with a DV

of +3␣ V. With DV

= +5␣ V and f

CLK IN

2.4576␣ MHz, the typical DV

current increases by 50␣ µA for a

crystal/resonator supplied clock versus an externally applied

clock. The ESR values for crystals and resonators at this fre-

quency tend to be low and as a result there tends to be little

difference between different crystal and resonator types.

When operating with a clock frequency of 1␣ MHz, the ESR

value for different crystal types varies significantly. As a result,

the DV

current drain varies across crystal types. When using

a crystal with an ESR of 700␣ Ω or when using a ceramic resona-

tor, the increase in the typical DV

current over an externally-

applied clock is 50␣ µA with DV

= +3␣ V and 175␣ µA with

= +5␣ V. When using a crystal with an ESR of 3␣ kΩ, the

increase in the typical DV

current over an externally applied

clock is again 50␣ µA with DV

= +3␣ V but 300␣ µA with

= +5␣ V.

The on-chip oscillator circuit also has a start-up time associated

with it before it is oscillating at its correct frequency and correct

voltage levels. The typical start up time for the circuit is 10␣ ms

with a DV

of +5␣ V and 15␣ ms with a DV

of +3␣ V. At 3␣ V

supplies, depending on the loading capacitances on the MCLK

pins, a 1␣ MΩ feedback resistor may be required across the crys-

tal or resonator in order to keep the start up times around the

15␣ ms duration.

The AD7714’s master clock appears on the MCLK OUT pin of

the device. The maximum recommended load on this pin is one

CMOS load. When using a crystal or ceramic resonator to gen-

erate the AD7714’s clock, it may be desirable to then use this

clock as the clock source for the system. In this case, it is recom-

mended that the MCLK OUT signal is buffered with a CMOS

buffer before being applied to the rest of the circuit.

System Synchronization

The SYNC input (or FSYNC bit) allows the user to reset the

modulator and digital filter without affecting any of the setup

conditions on the part. This allows the user to start gathering

samples of the analog input from a known point in time, i.e., the

rising edge of SYNC or when a 1 is written to FSYNC.

The SYNC input can also be used to allow two other functions.

If multiple AD7714s are operated from a common master clock,

they can be synchronized to update their output registers simul-

taneously. A falling edge on the SYNC input (or a 1 written to

the FSYNC bit of the Mode Register) resets the digital filter and

analog modulator and places the AD7714 into a consistent,

known state. While the SYNC input is low (or FSYNC high),

the AD7714 will be maintained in this state. On the rising edge

of SYNC (or when a 0 is written to the FSYNC bit), the modu-

lator and filter are taken out of this reset state and on the next

clock edge the part starts to gather input samples again. In a

system using multiple AD7714s, a common signal to their

SYNC inputs will synchronize their operation. This would nor-

mally be done after each AD7714 has performed its own cali-

bration or has had calibration coefficients loaded to it. The

output updates will then be synchronized with the maximum

possible difference between the output updates of the individual

AD7714s being one MCLK IN cycle.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P41

AD7714ARSZ-5REEL

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 3V/5V 500uA 24B Signal Condition

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AD7714ARSZ-5REEL

AD7714ARSZ-5REEL

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