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AD7853ARZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
FUNCTIONAL BLOCK DIAGRAM
2.5V
REFERENCE
CALIBRATION
MEMORY
AND CONTROLLER
SAR + ADC
CONTROL
AV
DD
AGND
DV
DD
DGND
CLKIN
CONVST
BUSY
SLEEP
CAL
C
REF2
C
REF1
REF
IN
/
REF
OUT
AIN(–)
AIN(+)
AMODE
SM1 SCLK
SYNC
POLARITYDOUTDINSM2
AGND
BUF
T/H
COMP
CHARGE
REDISTRIBUTION
DAC
SERIAL INTERFACE / CONTROL REGISTER
AD7853/AD7853L
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
3 V to 5 V Single Supply, 200 kSPS
12-Bit Sampling ADCs
AD7853/AD7853L*
FEATURES
Specified for V
DD
of 3 V to 5.5 V
Read-Only Operation
AD7853–200 kSPS; AD7853L–100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
Low Power:
AD7853: 12 mW (V
DD
= 3 V)
AD7853L: 4.5 mW (V
DD
= 3 V)
Automatic Power Down After Conversion (25 ␮W)
Flexible Serial Interface:
8051/SPI™/QSPI™/␮P Compatible
24-Lead DIP, SOIC and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
GENERAL DESCRIPTION
The AD7853/AD7853L are high speed, low power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the
AD7853 being optimized for speed and the AD7853L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system-calibration options to en-
sure accurate operation over time and temperature and have a
number of power-down options for low power applications.
The part powers up with a set of default conditions and can
operate as a read only ADC.
The AD7853 is capable of 200 kHz throughput rate while the
AD7853L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7853/AD7853L voltage
range is 0 to V
REF
with both straight binary and twos comple-
ment output coding. Input signal range is to the supply, and the
part is capable of converting full power signals to 100 kHz.
CMOS construction ensures low power dissipation of typically
4.5 mW for normal operation and 1.15 mW in power-down
mode, with a throughput rate of 10 kSPS (V
DD
= 3 V). The part
is available in 24-lead, 0.3 inch wide dual-in-line package
(DIP), 24-lead small outline (SOIC) and 24-lead small shrink
outline (SSOP) packages.
PRODUCT HIGHLIGHTS
1. Specified for 3 V and 5 V supplies.
2. Automatic calibration on power-up.
3. Flexible power management options including automatic
power-down after conversion.
4. Operates with reference voltages from 1.2 V to V
DD
.
5. Analog input ranges from 0 V to V
DD
.
6. Self- and system calibration.
7. Versatile serial I/O port (SPI/QSPI/8051/µP).
8. Lower power version AD7853L.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
*Patent pending.
SPI and QSPI are trademarks of Motorola, Incorporated.
Parameter A Version
1
B Version
1
Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio
3
70 71 dB min Typically SNR Is 72 dB
(SNR) V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz (100 kHz)
Total Harmonic Distortion (THD) –78 –78 dB max V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz (100 kHz)
Peak Harmonic or Spurious Noise –78 –78 dB max V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz (100 kHz)
Intermodulation Distortion (IMD)
Second Order Terms –78 –80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 200 kHz (100 kHz)
Third Order Terms –78 –80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 200 kHz (100 kHz)
DC ACCURACY
Resolution 12 12 Bits
Integral Nonlinearity ±1 ±1 LSB max 2.5 V External Reference V
DD
= 3 V, V
DD
= 5 V (B Grade Only)
±1 ±0.5 LSB max 5 V External Reference V
DD
= 5 V
(±1) LSB max (L Version, 5 V External Reference, V
DD
= 5 V)
(±1) LSB max (L Version)
Differential Nonlinearity ±1 ±1 LSB max Guaranteed No Missed Codes to 12 Bits. 2.5 V External Reference
V
DD
= 3 V, 5 V External Reference V
DD
= 5 V
Total Unadjusted Error ±1 ±1 LSB typ
Unipolar Offset Error ±1 ±1 LSB max 2.5 V External Reference V
DD
= 3 V, 5 V External Reference V
DD
= 5 V
Unipolar Offset Error (±2.5) (±2.5) LSB max (L Versions, 2.5 V External Reference V
DD
= 3 V, 5 V External
Reference V
DD
= 5 V)
Positive Full-Scale Error ±2.5 ±2.5 LSB max 2.5 V External Reference V
DD
= 3 V, 5 V External Reference V
DD
= 5 V
Positive Full-Scale Error (±4) (±4) LSB max (L Versions, 2.5 V External Reference V
DD
= 3 V, 5 V External
Reference V
DD
= 5 V)
Negative Full-Scale Error ±2.5 ±2.5 LSB max 2.5 V External Reference V
DD
= 3 V, 5 V External Reference V
DD
= 5 V
Negative Full-Scale Error (±4) (±4) LSB max (L Versions, 2.5 V External Reference V
DD
= 3 V, 5 V External
Reference V
DD
= 5 V)
Bipolar Zero Error ±2 ±2 LSB max 2.5 V External Reference V
DD
= 3 V, 5 V External Reference V
DD
= 5 V
Bipolar Zero Error (±2.5) (±2.5) LSB max (L Versions, 2.5 V External Reference V
DD
= 3 V, 5 V External
Reference V
DD
= 5 V)
ANALOG INPUT
Input Voltage Ranges 0 to V
REF
0 to V
REF
Volts i.e., AIN(+) – AIN(–) = 0 to V
REF
, AIN(–) Can Be Biased
Up But AIN(+) Cannot Go Below AIN(–)
±V
REF
/2 ±V
REF
/2 Volts i.e., AIN(+) – AIN(–) = –V
REF
/2 to +V
REF
/2, AIN(–) Should
Be Biased to +V
REF
/2 and AIN(+) Can Go Below AIN(–) But
Cannot Go Below 0 V
Leakage Current ±1 ±1 µA max
Input Capacitance 20 20 pF typ
REFERENCE INPUT/OUTPUT
REF
IN
Input Voltage Range 2.3/V
DD
2.3/V
DD
V min/max Functional from 1.2 V
Input Impedance 150 150 kΩ typ
REF
OUT
Output Voltage 2.3/2.7 2.3/2.7 V min/max
REF
OUT
Tempco 20 20 ppm/°C typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 2.4 V min AV
DD
= DV
DD
= 4.5 V to 5.5 V
2.1 2.1 V min AV
DD
= DV
DD
= 3.0 V to 3.6 V
Input Low Voltage, V
INL
0.8 0.8 V max AV
DD
= DV
DD
= 4.5 V to 5.5 V
0.6 0.6 V max AV
DD
= DV
DD
= 3.0 V to 3.6 V
Input Current, I
IN
±10 ±10 µA max Typically 10 nA, V
IN
= 0 V or V
DD
Input Capacitance, C
IN
4
10 10 pF max
AD7853/AD7853L–SPECIFICATIONS
1, 2
REV. B
–2–
(AV
DD
= DV
DD
= +3.0 V to +5.5 V, REF
IN
/REF
OUT
= 2.5 V
External Reference, f
CLKIN
= 4 MHz (1.8 MHz B Grade (0ⴗC to +70ⴗC), 1 MHz A and B Grades (–40ⴗC to +85ⴗC) for L Version); f
SAMPLE
= 200 kHz
(AD7853) 100 kHz (AD7853L); SLEEP = Logic High; T
A
= T
MIN
to T
MAX
, unless otherwise noted.) Specifications in () apply to the AD7853L.
Parameter A Version
1
B Version
1
Units Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
I
SOURCE
= 200 µA
4 4 V min AV
DD
= DV
DD
= 4.5 V to 5.5 V
2.4 2.4 V min AV
DD
= DV
DD
= 3.0 V to 3.6 V
Output Low Voltage, V
OL
0.4 0.4 V max I
SINK
= 0.8 mA
Floating-State Leakage Current ±10 ±10 µA max
Floating-State Output Capacitance
4
10 10 pF max
Output Coding Straight (Natural) Binary Unipolar Input Range
Twos Complement Bipolar Input Range
CONVERSION RATE
Conversion Time 4.6 (18) 4.6 (18) µs max (L Versions Only, –40°C to +85°C, 1 MHz CLKIN)
(10) µs max (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)
Track/Hold Acquisition Time 0.4 (1) 0.4 (1) µs min (L Versions Only)
POWER REQUIREMENTS
AV
DD,
DV
DD
+3.0/+5.5 +3.0/+5.5 V min/max
I
DD
Normal Mode
5
6 (1.9) 6 (1.9) mA max AV
DD
= DV
DD
= 4.5 V to 5.5 V. Typically 4.5 mA (1.5);
5.5 (1.9) 5.5 (1.9) mA max AV
DD
= DV
DD
= 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)
Sleep Mode
6
With External Clock On 10 10 µA typ Full Power-Down. Power Management Bits in Control Register
Set as PMGT1 = 1, PMGT0 = 0
400 400 µA typ Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
With External Clock Off 5 5 µA max Typically 1 µA. Full-Power Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 0
200 200 µA typ Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
Normal Mode Power Dissipation 33 (10.5) 33 (10.5) mW max V
DD
= 5.5 V: Typically 25 mW (8); SLEEP = V
DD
20 (6.85) 20 (6.85) mW max V
DD
= 3.6 V: Typically 15 mW (5.4); SLEEP = V
DD
Sleep Mode Power Dissipation
With External Clock On 55 55 µW typ V
DD
= 5.5 V; SLEEP = 0 V
36 36 µW typ V
DD
= 3.6 V; SLEEP = 0 V
With External Clock Off 27.5 27.5 µW max V
DD
= 5.5 V: Typically 5.5 µW; SLEEP = 0 V
18 18 µW max V
DD
= 3.6 V: Typically 3.6 µW; SLEEP = 0 V
SYSTEM CALIBRATION
Offset Calibration Span
7
+0.05 × V
REF
/–0.05 × V
REF
V max/min Allowable Offset Voltage Span for Calibration
Gain Calibration Span
7
+1.025 × V
REF
/–0.975 × V
REF
V max/min Allowable Full-Scale Voltage Span for Calibration
NOTES
1
Temperature ranges as follows: A, B Versions, –40°C to +85°C. For L Versions, A and B Versions f
CLKIN
= 1 MHz over –40°C to +85°C temperature range,
B Version f
CLKIN
= 1.8 MHz over 0°C to +70°C temperature range.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25°C to ensure compliance.
5
All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV
DD
. No load on the digital outputs.
Analog inputs @ AGND.
7
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7853/AD7853L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × V
REF
,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
REF
± 0.025 × V
REF
).
This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
AD7853/AD7853L
REV. B
–3–
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

AD7853ARZ-REEL

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Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 12B
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New from this manufacturer.
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