REV. B
–16–
AD7853/AD7853L
AIN(+)
AIN(–)
AMODE
AD7853/AD7853L
BIPOLAR
ANALOG
INPUT RANGE
SELECTED
DOUT
2S
COMPLEMENT
FORMAT
V
IN
= 0 TO V
REF
TRACK AND HOLD
AMPLIFIER
V
REF
/2
DV
DD
Figure 15.
±
V
REF
/2 about V
REF
/2 Bipolar Input Configuration
+FS –1LSB
OUTPUT
CODE
0V
111...111
111...110
111...101
111...100
000...011
000...001
000...000
000...010
V
IN
= (AIN(+) – AIN(–)), INPUT VOLTAGE
1LSB
1LSB =
FS
4096
Figure 16. Unipolar Transfer Characteristic
Figure 15 shows the AD7853/AD7853L’s ±V
REF
/2 bipolar ana-
log input configuration (where AIN(+) cannot go below 0 V so
for the full bipolar range then the AIN(–) pin should be biased
to +V
REF
/2). Once again the designed code transitions occur
midway between successive integer LSB values. The output
coding is twos complement with 1 LSB = 4096 = 3.3 V/4096 =
0.8 mV. The ideal input/output transfer characteristic is shown
in Figure 17.
– 1 LSB
FS = V
REF
V
1LSB =
FS
4096
OUTPUT
CODE
V
REF
/2
011...111
011...110
000...001
000...000
100...001
100...000
100...010
V
IN
= (AIN(+) – AIN(–)), INPUT VOLTAGE
0V
+ FS
111...111
(V
REF
/2) –1 LSB
(V
REF
/2) +1 LSB
Figure 17. Bipolar Transfer Characteristic
IC1
AD820
AD820-3V
0.1mF
10mF
V+
V–
10kV
50V
10nF
(NPO)
TO AIN(+) OF
AD7853/AD7853L
V
IN
–V
REF
/2 TO +V
REF
/2
V
REF
/2
10kV
10kV
10kV
+3V TO +5V
Figure 13. Analog Input Buffering
Input Ranges
The analog input range for the AD7853/AD7853L is 0 V to
V
REF
in both the unipolar and bipolar ranges.
The only difference between the unipolar range and the bipolar
range is that in the bipolar range the AIN(–) has to be biased up
to +V
REF
/2 and the output coding is twos complement (See
Table V and Figures 14 and 15). The unipolar or bipolar mode
is selected by the AMODE pin (0 for the unipolar range and 1
for the bipolar range).
Table V. Analog Input Connections
Analog Input Input Connections Connection
Range AIN(+) AIN(–) Diagram AMODE
0 V to V
REF
1
V
IN
AGND Figure 14 DGND
±V
REF
/2
2
V
IN
V
REF
/2 Figure 15 DV
DD
NOTES
1
Output code format is straight binary.
2
Range is ±V
REF
/2 biased about V
REF
/2. Output code format is twos complement.
Note that the AIN(–) pin on the AD7853/AD7853L can be
biased up above AGND in the unipolar mode also, if required.
The advantage of biasing the lower end of the analog input
range away from AGND is that the user does not have to have
the analog input swing all the way down to AGND. This has the
advantage in true single supply applications that the input am-
plifier does not have to swing all the way down to AGND. The
upper end of the analog input range is shifted up by the same
amount. Care must be taken so that the bias applied does not
shift the upper end of the analog input above the AV
DD
supply.
In the case where the reference is the supply, AV
DD
, the AIN(–)
must be tied to AGND in unipolar mode.
AIN(+)
AIN(–)
AMODE
AD7853/AD7853L
UNIPOLAR ANALOG
INPUT RANGE
SELECTED
DOUT
STRAIGHT
BINARY
FORMAT
V
IN
= 0 TO V
REF
TRACK AND HOLD
AMPLIFIER
Figure 14. 0 to V
REF
Unipolar Input Configuration
Transfer Functions
For the unipolar range the designed code transitions occur
midway between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is
straight binary for the unipolar range with 1 LSB = FS/4096 =
3.3 V/4096 = 0.8 mV when V
REF
= 3.3 V. The ideal input/output
transfer characteristic for the unipolar range is shown in
Figure 16.
REV. B
–17–
AD7853/AD7853L
REFERENCE SECTION
For specified performance, it is recommended that when using
an external reference this reference should be between 2.3 V
and the analog supply AV
DD
. The connections for the relevant
reference pins are shown in the typical connection diagrams. If
the internal reference is being used, the REF
IN
/REF
OUT
pin
should have a 100 nF capacitor connected to AGND very close
to the REF
IN
/REF
OUT
pin. These connections are shown in
Figure 18.
If the internal reference is required for use external to the ADC,
it should be buffered at the REF
IN
/REF
OUT
pin and a 100 nF
connected from this pin to AGND. The typical noise performance
for the internal reference, with 5 V supplies is 150 nV/Hz @
1 kHz and dc noise is 100 µV p-p.
AV
DD
DV
DD
C
REF1
C
REF2
REF
IN
/REF
OUT
ANALOG SUPPLY
+3V TO +5V
0.1mF10mF
0.1mF
0.01mF
0.1mF
0.1mF
AD7853/AD7853L
Figure 18. Relevant Connections When Using Internal
Reference
The other option is that the REF
IN
/REF
OUT
pin be overdriven
by connecting it to an external reference. This is possible due to
the series resistance from the REF
IN
/REF
OUT
pin to the internal
reference. This external reference can have a range that includes
AV
DD
. When using AV
DD
as the reference source, the 100 nF
capacitor from the REF
IN
/REF
OUT
pin to AGND should be as
close as possible to the REF
IN
/REF
OUT
pin, and also the C
REF1
pin should be connected to AV
DD
to keep this pin at the same
level as the reference. The connections for this arrangement are
shown in Figure 19. When using AV
DD
it may be necessary to
add a resistor in series with the AV
DD
supply. This will have the
effect of filtering the noise associated with the AV
DD
supply.
AV
DD
DV
DD
C
REF1
C
REF2
REF
IN
/REF
OUT
ANALOG SUPPLY
+3V TO +5V
0.1mF
10mF
0.1mF
0.01mF
0.1mF
0.1mF
AD7853/AD7853L
Figure 19. Relevant Connections When Using AV
DD
as the
Reference
PERFORMANCE CURVES
Figure 20 shows a typical FFT plot for the AD7853 at 200 kHz
sample rate and 10 kHz input frequency.
0
–120
–60
–100
20
–80
0
–20
–40
806040
AV
DD
= DV
DD
= 3.3V
f
SAMPLE
= 200kHz
f
IN
= 10kHz
SNR = 72.04dB
THD = –88.43dB
FREQUENCY – kHz
100
SNR – dB
Figure 20. FFT Plot
Figure 21 shows the SNR versus Frequency for different sup-
plies and different external references.
INPUT FREQUENCY – kHz
74
73
69
0 100
S(N+D) RATIO – dB
20 40 60 80
72
71
70
5.0V SUPPLIES, WITH 5V REFERENCE
5.0V SUPPLIES
5.0V SUPPLIES, L VERSION
3.3V SUPPLIES
AV
DD
= DV
DD
WITH 2.5V REFERENCE
UNLESS STATED OTHERWISE
Figure 21. SNR vs. Frequency
Figure 22 shows the Power Supply Rejection Ratio versus Fre-
quency for the part. The Power Supply Rejection Ratio is de-
fined as the ratio of the power in ADC output at frequency f to
the power of a full-scale sine wave.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power of a full-
scale sine wave. Here a 100 mV peak-to-peak sine wave is
coupled onto the AV
DD
supply while the digital supply is left
unaltered. Both the 3.3 V and 5.0 V supply performances are
shown.
REV. B
–18–
AD7853/AD7853L
is powered down and I
DD
is 400 µA typ. The choice of full or par-
tial power-down does not give any significant improvement in
throughput with a power-down between conversions. This is
discussed in the next section–Power-Up Times. However, a
partial power-down does allow the on-chip reference to be used
externally even though the rest of the AD7853 circuitry is pow-
ered down. It also allows the AD7853 to be powered up faster
after a long power-down period when using the on-chip refer-
ence (See Power-Up Times–Using On-Chip Reference).
When using the SLEEP pin, the power management bits PMGT1
and PMGT0 should be set to zero (default status on power-up).
Bringing the SLEEP pin logic high ensures normal operation,
and the part does not power down at any stage. This may be
necessary if the part is being used at high throughput rates when
it is not possible to power down between conversions. If the user
wishes to power down between conversions at lower throughput
rates (i.e. <100 kSPS for the AD7853) to achieve better power
performances, then the SLEEP pin should be tied logic low.
If the power-down options are to be selected in software only,
then the SLEEP pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a Full Power-Down, Full Power-Up, Full Power-
Down Between Conversions, and a Partial Power-Down Be-
tween Conversions can be selected.
A typical connection diagram for a low power application is
shown in Figure 23 (AD7853L is the low power version of the
AD7853).
INPUT FREQUENCY – kHz
–78
–80
–90
0 100
PSRR – dB
20 40 60 80
–82
–84
–86
5.0V
3.3V
AV
DD
= DV
DD
= 3.3V/5.0V,
100mV p-p SINE WAVE ON AV
DD
–88
Figure 22. PSRR vs. Frequency
POWER-DOWN OPTIONS
The AD7853 provides flexible power management to allow the
user to achieve the best power performance for a given through-
put rate. The power management options are selected by
programming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the SLEEP pin. Table VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware or a
combination of both. The AD7853 can be fully or partially
powered down. When fully powered down, all the on-chip cir-
cuitry is powered down and I
DD
is 1 µA typ. If a partial power-
down is selected, then all the on-chip circuitry except the reference
AV
DD
DV
DD
AIN(+)
AIN(–)
AMODE
C
REF1
C
REF2
SLEEP
DIN
DOUT
SYNC
SM1
SM2
CONVST
AGND
DGND
CLKIN
SCLK
REF
IN
/REF
OUT
POLARITY
AD7853L
0.1mF
0.1mF
10mF
DV
DD
UNIPOLAR RANGE
0.1mF
0.01mF
SERIAL MODE
SELECTION BITS
MASTER CLOCK INPUT
CONVERSION
START INPUT
SERIAL DATA OUTPUT
0.1mF
CAL
0.01mF
INTERNAL
REFERENCE
0V TO 2.5V
INPUT
1.8MHz OSCILLATOR
SERIAL CLOCK INPUT
100kHz PULSE
GENERATOR
DIN AT DGND
=> NO WRITING
TO DEVICE
AUTO POWER-
DOWN AFTER
CONVERSION
THREE-WIRE
MODE
SELECTED
LOW POWER
mC/mP
AUTO CAL ON
POWER-UP
CURRENT, I = 1.5mA TYP
REF-192
ANALOG SUPPLY
+3V
OPTIONAL EXTERNAL
REFERENCE
Figure 23. Typical Low Power Circuit

AD7853ARZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 12B
Lifecycle:
New from this manufacturer.
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