AD7853ARZ-REEL Datasheet AD7853ARZ, AD7853LARSZ, AD7853ARZ-REEL | P31-P33

REV. B

–31–

AD7853/AD7853L

68HC11/L11/16

SCK

CONVST

CLKIN

SCLK

DOUT

BUSY

SM1

SM2

POLARITY

OPTIONAL

4MHz/1.8MHz

SYNC

MISO

DIN AT DGND FOR

NO WRITING TO PART

MASTER

SLAVE

DIN

OPTIONAL

IRQ

MOSI

DGND FOR HC11, SPI

FOR HC16, QSPI

SPI

HC16, QSPI

AD7853/AD7853L

Figure 46. 68HC11 and 68HC16 Interface

AD7853/AD7853L to ADSP-21xx Interface

Figure 47 shows the AD7853/AD7853L interface to the ADSP-

21xx. The ADSP-21xx is the slave and the AD7853/AD7853L

is the master. The AD7853/AD7853L is in Interface Mode 5.

For the ADSP-21xx, the bits in the serial port control register

should be set up as TFSR = RFSR = 1 (need a frame sync for

every transfer), SLEN = 15 (16-bit word length), TFSW =

RFSW = 1 (alternate framing mode for transmit and receive

operations), INVRFS = INVTFS = 1 (active low RFS and

TFS), IRFS = ITFS = 0 (External RFS and TFS), and ISCLK

= 0 (external serial clock). The CLKIN and CONVST signals

could be supplied from the ADSP-21xx or from an external

source. The AD7853/AD7853L supplies the SCLK and the

SYNC signals to the ADSP-21xx and the reading and writing

takes place during conversion. The BUSY signal only indicates

when the conversion is finished and may not be required. The

data access and hold times of the ADSP-21xx and the AD7853/

AD7853L allows for a CLKIN of 4 MHz/1.8 MHz at both 5 V

and 3 V supplies.

ADSP-21xx

SCK

AD7853/AD7853L

CONVST

CLKIN

SCLK

DOUT

BUSY

SM1

SM2

POLARITY

OPTIONAL

4MHz/1.8MHz

SYNC

RFS

DIN AT DGND FOR

NO WRITING TO PART

SLAVE

MASTER

OPTIONAL

DIN

OPTIONAL

IRQ

TFS

Figure 47. ADSP-21xx Interface

AD7853/AD7853L to DSP56000/1/2/L002 Interface

Figure 48 shows the AD7853/AD7853L to DSP56000/1/2/L002

interface. Here the DSP5600x is the master and the AD7853/

AD7853L is the slave. The AD7853/AD7853L is in Interface

Mode 3. The DSP56L002 is used when the AD7853/AD7853L

is being operated at 3 V. The setting of the bits in the registers

of the DSP5600x would be for synchronous operation (SYN =

1), internal frame sync (SCD2 = 1), Internal clock (SCKD =

1), 16-bit word length (WL1 = 1, WL0 = 0), frames sync only

active at beginning of the transfer (FSL1 = 0, FSL0 = 1). A

gated clock can be used (GCK = 1) or if the SCLK is to be tied

to the CLKIN of the AD7853/AD7853L, then there must be a

continuous clock (GCK = 0). Again the data access and hold

times of the DSP5600x and the AD7853/AD7853L should

allow for an SCLK of 4 MHz/1.8 MHz.

DSP

56000/1/2/L002

SRD

SCK

AD7853/AD7853L

CONVST

CLKIN

SCLK

DOUT

BUSY

SM1

SM2

POLARITY

OPTIONAL

4MHz/1.8MHz

SYNC

SC2

DIN AT DGND FOR

NO WRITING TO PART

MASTER

SLAVE

OPTIONAL

DIN

OPTIONAL

IRQ

STD

Figure 48. DSP56000/1/2 Interface

AD7853/AD7853L to TMS320C20/25/5x/LC5x Interface

Figure 49 shows the AD7853/AD7853L to the TMS320Cxx

interface. The TMS320LC5x is used when the AD7853/AD7853L

is being operated at 3 V. The AD7853/AD7853L is the master

and operates in Interface Mode 5. For the TMS320Cxx the

CLKX, CLKR, FSX, and FSR pins should all be configured as

inputs. The CLKX and the CLKR should be connected to-

gether as should the FSX and FSR. Since the AD7853/AD7853L

is the master and the reading and writing occurs during the

conversion, the BUSY only indicates when the conversion is

finished and thus may not be required. Again the data access

and hold times of the TMS320Cxx and the AD7853/AD7853L

allows for a CLKIN of 4 MHz/1.8 MHz.

TMS320C20/

25/5x/LC5x

CLKR

AD7853/AD7853L

CONVST

CLKIN

SCLK

DOUT

BUSY

SM1

SM2

POLARITY

OPTIONAL

4MHz/1.8MHz

SYNCFSR

DIN AT DGND FOR

NO WRITING TO PART

SLAVE

MASTER

OPTIONAL

DIN

OPTIONAL

INT0

FSX

CLKX

Figure 49. TMS320C20/25/5x Interface

REV. B

–32–

AD7853/AD7853L

APPLICATION HINTS

Grounding and Layout

The analog and digital supplies to the AD7853/AD7853L are

independent and separately pinned out to minimize coupling

between the analog and digital sections of the device. The part

has very good immunity to noise on the power supplies as can

be seen by the PSRR vs. Frequency graph. However, care

should still be taken with regard to grounding and layout.

The printed circuit board that houses the AD7853/AD7853L

should be designed such that the analog and digital sections are

separated and confined to certain areas of the board. This facili-

tates the use of ground planes that can be separated easily. A

minimum etch technique is generally best for ground planes as it

gives the best shielding. Digital and analog ground planes

should only be joined in one place. If the AD7853/AD7853L is

the only device requiring an AGND to DGND connection, then

the ground planes should be connected at the AGND and

DGND pins of the AD7853/AD7853L. If the AD7853/AD7853L

is in a system where multiple devices require AGND to DGND

connections, the connection should still be made at one point

only, a star ground point which should be established as close as

possible to the AD7853/AD7853L.

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7853/AD7853L to avoid noise coupling.

The power supply lines to the AD7853/AD7853L should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals like clocks should be shielded with digital

ground to avoid radiating noise to other sections of the board

and clock signals should never be run near the analog inputs.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

will reduce the effects of feedthrough through the board. A

microstrip technique is by far the best but is not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to ground planes while signals are

placed on the solder side.

Good decoupling is also important. All analog supplies should

be decoupled with 10␣ µF tantalum in parallel with 0.1␣ µF ca-

pacitors to AGND. All digital supplies should have a 0.1␣ µF disc

ceramic capacitor to AGND. To achieve the best from these

decoupling components, they must be placed as close as pos-

sible to the device, ideally right up against the device. In systems

where a common supply voltage is used to drive both the AV

and DV

of the AD7853/AD7853L, it is recommended that

the system’s AV

supply is used. In this case there should be a

10 Ω resistor between the AV

pin and DV

pin. This supply

should have the recommended analog supply decoupling capaci-

tors between the AV

pin of the AD7853/AD7853L and

AGND and the recommended digital supply decoupling ca-

pacitor between the DV

pin of the AD7853/AD7853L and

DGND.

Evaluating the AD7853/AD7853L Performance

The recommended layout for the AD7853/AD7853L is outlined

in the evaluation board for the AD7853/AD7853L. The evalua-

tion board package includes a fully assembled and tested evalua-

tion board, documentation, and software for controlling the

board from the PC via the EVAL-CONTROL BOARD. The

EVAL-CONTROL BOARD can be used in conjunction with

the AD7853/AD7853L evaluation board, as well as many other

Analog Devices evaluation boards ending in the CB designator,

to demonstrate/evaluate the ac and dc performance of the

AD7853/AD7853L.

The software allows the user to perform ac (fast Fourier trans-

form) and dc (histogram of codes) tests on the AD7853/AD7853L.

It also gives full access to all the AD7853/AD7853L on-chip

registers allowing for various calibration and power-down op-

tions to be programmed.

AD785x Family

All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V.

AD7853 – Single Channel Serial

AD7854 – Single Channel Parallel

AD7858 – Eight Channel Serial

AD7859 – Eight Channel Parallel

REV. B

–33–

AD7853/AD7853L

PAGE INDEX

Topic Page

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4

TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 9

Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 12

Addressing the Calibration Registers . . . . . . . . . . . . . . . . 12

Writing to/Reading from the Calibration Registers . . . . . . 12

Adjusting the Offset Calibration Register . . . . . . . . . . . . . 13

Adjusting the Gain Calibration Register . . . . . . . . . . . . . . 13

CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 14

CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . 15

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PERFORMANCE CURVES . . . . . . . . . . . . . . . . . . . . . . . . 17

POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 18

POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 19

Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 19

POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 20

CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . 20

Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 20

Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 20

Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21

System Calibration Description . . . . . . . . . . . . . . . . . . . . 21

System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22

System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 22

SERIAL INTERFACE SUMMARY . . . . . . . . . . . . . . . . . . 23

Resetting the Serial Interface . . . . . . . . . . . . . . . . . . . . . . 23

DETAILED TIMING SECTION . . . . . . . . . . . . . . . . . . . 24

Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 24

Mode 2 (3-Wire SPI/QSPI Interface Mode) . . . . . . . . . . . 25

Mode 3 (QSPI Interface Mode) . . . . . . . . . . . . . . . . . . . . 25

Modes 4 and 5 (Self-Clocking Modes) . . . . . . . . . . . . . . . 25

CONFIGURING THE AD7853/AD7853L . . . . . . . . . . . . 27

AD7853/AD7853L as a Read-Only ADC . . . . . . . . . . . . 27

Writing to the AD7853/AD7853L . . . . . . . . . . . . . . . . . . 28

Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 28

Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 29

Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 29

MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 30

AD7853/AD7853L to 8XC51/PIC17C42 Interface . . . . . 30

AD7853/AD7853L to 68HC11/16/L11/PIC16C42

Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

AD7853/AD7853L to ADSP-21xx Interface . . . . . . . . . . 31

AD7853/AD7853L to DSP56000/1/2/L002 Interface . . . 31

AD7853/AD7853L to TMS320C20/25/5x/LC5x

Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

APPLICATION HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Evaluating the AD7853/AD7853L Performance . . . . . . . 32

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34

TABLE INDEX

# Title Page

I. Write Register Addressing . . . . . . . . . . . . . . . . . . . . . . 9

II. Read Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 9

III. Calibration Selection . . . . . . . . . . . . . . . . . . . . . . . . . 10

IV. Calibrating Register Addressing . . . . . . . . . . . . . . . . . 12

V. Analog Input Connections . . . . . . . . . . . . . . . . . . . . . 16

VI. Power Management Options . . . . . . . . . . . . . . . . . . . 19

VII. Power Consumption vs. Throughput . . . . . . . . . . . . . 20

VIII. Calibration Times . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

IX. SCLK Active Edge for Different Interface Modes . . . 23

X. Interface Mode Description . . . . . . . . . . . . . . . . . . . . 23

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

AD7853ARZ-REEL

Mfr. #:

Buy AD7853ARZ-REEL

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 12B

Lifecycle:

New from this manufacturer.

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AD7853ARZ-REEL

AD7853ARZ-REEL

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