REV. B
–4–
AD7853/AD7853L
TIMING SPECIFICATIONS
1
Limit at T
MIN
, T
MAX
(A, B Versions)
Parameter 5 V 3 V Units Description
f
CLKIN
2
500 500 kHz min Master Clock Frequency
4 4 MHz max
1.8 1.8 MHz max L Version, 0°C to +70°C, B Grade Only
1 1 MHz max L Version, –40°C to +85°C
f
SCLK
3
4 4 MHz max Interface Modes 1, 2, 3 (External Serial Clock)
f
CLKIN
f
CLKIN
MHz max Interface Modes 4, 5 (Internal Serial Clock)
t
1
4
100 100 ns min CONVST Pulsewidth
t
2
50 90 ns max CONVST↓ to BUSY↑ Propagation Delay
t
CONVERT
4.6 4.6 µs max Conversion Time = 18 t
CLKIN
10 (18) 10 (18) µs max L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 t
CLKIN
t
3
–0.4 t
SCLK
–0.4 t
SCLK
ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
⫿0.4 t
SCLK
⫿0.4 t
SCLK
ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
t
4
0.6 t
SCLK
0.6 t
SCLK
ns min SYNC↓ to SCLK↓ Setup Time. Interface Mode 4 Only
t
5
5
50 90 ns max Delay from SYNC↓ until DOUT 3-State Disabled
t
5A
5
50 90 ns max Delay from SYNC↓ until DIN 3-State Disabled
t
6
5
75 115 ns max Data Access Time After SCLK↓
t
7
40 60 ns min Data Setup Time Prior to SCLK↑
t
8
20 30 ns min Data Valid to SCLK Hold Time
t
9
6
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK High Pulsewidth (Interface Modes 4 and 5)
t
10
6
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK Low Pulsewidth (Interface Modes 4 and 5)
t
11
30 50 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 t
SCLK
50/0.4 t
SCLK
ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3
t
11A
50 50 ns max SCLK↑ to SYNC↑ Hold Time
t
12
7
50 50 ns max Delay from SYNC↑ until DOUT 3-State Enabled
t
13
90 130 ns max Delay from SCLK↑ to DIN Being Configured as Output
t
14
8
50 90 ns max Delay from SCLK↑ to DIN Being Configured as Input
t
15
2.5 t
CLKIN
2.5 t
CLKIN
ns max CAL↑ to BUSY↑ Delay
t
16
2.5 t
CLKIN
2.5 t
CLKIN
ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence
t
CAL
9
31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent
(125013 t
CLKIN
)
t
CAL1
9
27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111114 t
CLKIN
)
t
CAL2
9
3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent
(13899 t
CLKIN
)
NOTES
Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of
SCLK will apply.
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
For Interface Modes 1, 2, 3 the SCLK max frequency will be 4 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f
CLKIN
.
4
The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply (see Power-
Down section).
5
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t
SCLK
= 0.5 t
CLKIN
.
7
t
12
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.
8
t
14
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part
in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.
9
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.
Specifications subject to change without notice.
(AV
DD
= DV
DD
= +3.0 V to +5.5 V; f
CLKIN
= 4 MHz for AD7853 and 1.8/1 MHz for AD7853L; T
A
= T
MIN
to
T
MAX
, unless otherwise noted)
