AD7853ARZ-REEL Datasheet AD7853ARZ, AD7853LARSZ, AD7853ARZ-REEL | P7-P9

REV. B

–7–

AD7853/AD7853L

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1 CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode and

starts conversion. When this input is not used, it should be tied to DV

2 BUSY Busy Output. The busy output is triggered high by the falling edge of

CONVST or rising edge of CAL, and

remains high until conversion is completed. BUSY is also used to indicate when the AD7853/AD7853L has

completed its on-chip calibration sequence.

3 SLEEP Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down including the

internal voltage reference provided there is no conversion or calibration being performed. Calibration data

is retained. A Logic 1 results in normal operation. See Power-Down section for more details.

4 REF

/ Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

REF

OUT

reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears

at the pin. This pin can be overdriven by an external reference or can be taken as high as AV

. When this

pin is tied to AV

, or when an externally applied reference approaches AV

, the C

REF1

pin should also be

tied to AV

5AV

Analog Positive Supply Voltage, +3.0 V to +5.5 V.

6, 12 AGND Analog Ground. Ground reference for track/hold, reference and DAC.

REF1

Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the

internal DAC. The capacitor should be tied between the pin and AGND.

REF2

Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip

reference. The capacitor should be tied between the pin and AGND.

9 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above

at any time, and cannot go below AIN(–) when the unipolar input range is selected.

10 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above

at any time.

11 NC No Connect Pin.

13 AMODE Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range

0 to V

REF

(i.e., AIN(+) – AIN(–) = 0 to V

REF

). In this case AIN(+) cannot go below AIN(–) and

AIN(–) cannot go below AGND. A Logic 1 selects range –V

REF

/2 to +V

REF

/2 (i.e., AIN(+) – AIN(–) =

–V

REF

/2 to +V

REF

/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to

REF

/2 to allow AIN(+) to go from 0 V to +V

REF

14 POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will

reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high

and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and

Table IX for the SCLK active edges.

15 SM1 Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-

tion as described in Table X.

16 SM2 Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-

tion as described in Table X.

17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets

all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a

10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input

overrides all other internal operations. If the autocalibration is not required, this pin should be tied to a

logic high.

18 DV

Digital Supply Voltage, +3.0 V to +5.5 V.

19 DGND Digital Ground. Ground reference point for digital circuitry.

20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.

21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act

as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).

22 CLKIN Master Clock Signal for the device (4 MHz for AD7853, 1.8 MHz for AD7853L). Sets the conversion and

calibration times.

23 SCLK Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the

type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and

SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.

24 SYNC This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync

in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X).

REV. B

–8–

AD7853/AD7853L

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7853/AD7853L, it is

defined as:

THD (dB) = 20 log

)

where V

is the rms amplitude of the fundamental and V

, V

and V

are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for parts

where the harmonics are buried in the noise floor, it will be a

noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are

those for which neither m nor n are equal to zero. For example,

the second order terms include (fa + fb) and (fa – fb), while the

third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and

(fa – 2fb).

Testing is performed using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used. In

this case, the second order terms are usually distanced in fre-

quency from the original sine waves while the third order terms

are usually at a frequency close to the input frequencies. As a

result, the second and third order terms are specified separately.

The calculation of the intermodulation distortion is as per the

THD specification where it is the ratio of the rms sum of the

individual distortion products to the rms amplitude of the sum

of the fundamentals expressed in dBs.

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale, a point 1/2 LSB

below the first code transition, and full scale, a point 1/2 LSB

above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Total Unadjusted Error

This is the deviation of the actual code from the ideal code

taking all errors into account (Gain, Offset, Integral Nonlinearity,

and other errors) at any point along the transfer function.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)

when operating in the unipolar mode.

Positive Full-Scale Error

This applies to the unipolar and bipolar modes and is the devia-

tion of the last code transition from the ideal AIN(+) voltage

(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been

adjusted out.

Negative Full-Scale Error

This applies to the bipolar mode only and is the deviation of the

first code transition (10 . . . 000 to 10 . . . 001) from the ideal

AIN(+) voltage (AIN(–) – V

REF

/2 + 0.5 LSB).

Bipolar Zero Error

This is the deviation of the midscale transition (all 1s to all 0s)

from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode and the end of

conversion. Track/Hold acquisition time is the time required for

the output of the track/hold amplifier to reach its final value,

within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the sum of all nonfundamental sig-

nals up to half the sampling frequency (f

/2), excluding dc. The

ratio is dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the quantiza-

tion noise. The theoretical signal to (noise + distortion) ratio for

an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N +1.76) dB

Thus for a 12-bit converter, this is 74 dB.

REV. B

–9–

AD7853/AD7853L

ON-CHIP REGISTERS

The AD7853/AD7853L powers up with a set of default conditions, and the user need not ever write to the device. In this case the

AD7853/AD7853L will operate as a Read-Only ADC. The AD7853/AD7853L still retains the flexibility for performing a full power-

down, and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7853/AD7853L as a Read-

Only ADC.

Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-

bration, and software conversion start can be selected by writing to the part.

The AD7853/AD7853L contains a Control register, ADC output data register, Status register, Test register and 10 Calibra-

tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and

calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7853/AD7853L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine

which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are writ-

ten that the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the over-

all write register hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

0 0 This combination does not address any register so the subsequent 14 data bits are ignored.

0 1 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.

1 0 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written

to the selected calibration register.

1 1 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the

control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These

bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address

bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be

from the ADC output data register.

Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register

until the read selection bits are changed in the control register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0 0 All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up

default setting. There will always be four leading zeros when reading from the ADC output data register.

0 1 All successive read operations will be from TEST REGISTER.

1 0 All successive read operations will be from CALIBRATION REGISTERS.

1 1 All successive read operations will be from STATUS REGISTER.

ADDR1, ADDR0

DECODE

CALIBRATION

REGISTERS

GAIN(1)

OFFSET(1)

10 11

CALSLT1, CALSLT0

DECODE

00 01 10 11

TEST

CONTROL

OFFSET(1)

GAIN(1)

OFFSET(1)

DAC(8)

Figure 4. Write Register Hierarchy/Address Decoding

RDSLT1, RDSLT0

DECODE

CALIBRATION

REGISTERS

GAIN(1)

OFFSET(1)

10 11

CALSLT1, CALSLT0

DECODE

00 01 10 11

TEST

STATUS

OFFSET(1)

GAIN(1)

OFFSET(1)

DAC(8)

ADC OUTPUT

DATA REGISTER

Figure 5. Read Register Hierarchy/Address Decoding

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

AD7853ARZ-REEL

Mfr. #:

Buy AD7853ARZ-REEL

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 12B

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7853ARZ-REEL

AD7853ARZ-REEL

Products related to this Datasheet