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AD7853ARZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
REV. B
–22–
AD7853/AD7853L
System Gain and Offset Interaction
The inherent architecture of the AD7853/AD7853L leads to an
interaction between the system offset and gain errors when a
system calibration is performed. Therefore it is recommended to
perform the cycle of a system offset calibration followed by a
system gain calibration twice. Separate system offset and system
gain calibrations reduce the offset and gain errors to at least the
12-bit level. By performing a system offset calibration first and a
system gain calibration second, priority is given to reducing the
gain error to zero before reducing the offset error to zero. If the
system errors are small, a system offset calibration would be
performed, followed by a system gain calibration. If the systems
errors are large (close to the specified limits of the calibration
range), this cycle would be repeated twice to ensure that the
offset and gain errors were reduced to at least the 12-bit level.
The advantage of doing separate system offset and system gain
calibrations is that the user has more control over when the
analog inputs need to be at the required levels, and the CONVST
signal does not have to be used.
Alternatively, a system (gain + offset) calibration can be per-
formed. It is recommended to perform three system (gain +
offset) calibrations to reduce the offset and gain errors to the
12-bit level. For the system (gain + offset) calibration priority is
given to reducing the offset error to zero before reducing the
gain error to zero. Thus if the system errors are small then two
system (gain + offset) calibrations will be sufficient. If the sys-
tem errors are large (close to the specified limits of the calibra-
tion range), three system (gain + offset) calibrations may be
required to reduced the offset and gain errors to at least the
12-bit level. There will never be any need to perform more than
three system (offset + gain) calibrations.
In Bipolar Mode the midscale error is adjusted for an offset
calibration and the positive full-scale error is adjusted for the
gain calibration; in Unipolar Mode the zero-scale error is ad-
justed for an offset calibration and the positive full-scale error is
adjusted for a gain calibration.
System Calibration Timing
The calibration timing diagram in Figure 31 is for a full system
calibration where the falling edge of CAL initiates an internal
reset before starting a calibration (note that if the part is in power-
down mode the CAL pulsewidth must take account of the power-up
time). If a full system calibration is to be performed in software,
it is easier to perform separate gain and offset calibrations so
that the CONVST bit in the control register does not have to be
programmed in the middle of the system calibration sequence.
The rising edge of CAL starts calibration of the internal DAC
and causes the BUSY line to go high. If the control register is
set for a full system calibration, the CONVST must be used
also. The full-scale system voltage should be applied to the
analog input pins from the start of calibration. The BUSY line
will go low once the DAC and system gain calibration are
complete. Next the system offset voltage is applied to the AIN
pin for a minimum setup time (t
SETUP
) of 100 ns before the
rising edge of the CONVST and remain until the BUSY signal
goes low. The rising edge of the CONVST starts the system
offset calibration section of the full system calibration and also
causes the BUSY signal to go high. The BUSY signal will go
low after a time t
CAL2
when the calibration sequence is complete.
The timing for a system (gain + offset) calibration is very similar
to that of Figure 31, the only difference being that the time
t
CAL1
will be replaced by a shorter time of the order of t
CAL2
as
the internal DAC will not be calibrated. The BUSY signal will
signify when the gain calibration is finished and when the part is
ready for the offset calibration.
t
1
= 100ns MIN,
t
14
= 50/90ns MIN 5V/3V,
t
15
= 2.5
t
CLKIN
MAX,
t
CAL1
= 111114
t
CLKIN
MAX,
t
CAL2
= 13899
t
CLKIN
(I/P)
BUSY (O/P)
(I/P)
t
1
AIN (I/P)
t
15
t
CAL1
t
CAL2
t
16
t
SETUP
V
SYSTEM FULL SCALE
V
OFFSET
Figure 31. Timing Diagram for Full System Calibration
The timing diagram for a system offset or system gain calibra-
tion is shown in Figure 32. Here again the CAL is pulsed and
the rising edge of the CAL initiates the calibration sequence (or
the calibration can be initiated in software by writing to the
control register). The rising edge of the CAL causes the BUSY
line to go high and it will stay high until the calibration sequence is
finished. The analog input should be set at the correct level for a
minimum setup time (t
SETUP
) of 100 ns before the rising edge of
CAL and stay at the correct level until the BUSY signal goes
low.
(I/P)
BUSY (O/P)
AIN (I/P)
t
15
t
SETUP
t
1
t
CAL2
V
SYSTEM FULL SCALE
OR V
SYSTEM OFFSET
Figure 32. Timing Diagram for System Gain or System
Offset Calibration
REV. B
–23–
AD7853/AD7853L
SERIAL INTERFACE SUMMARY
Table IX details the five interface modes and the serial clock
edges from which the data is clocked out by the AD7853/
AD7853L (DOUT Edge) and that the data is latched in on
(DIN Edge). The logic level of the POLARITY pin is shown
and it is clear that this reverses the edges.
In Interface Modes 4 and 5 the SYNC always clocks out the
first data bit and SCLK will clock out the subsequent bits.
In Interface Modes 1, 2, and 3 the SYNC is gated with the
SCLK and the POLARITY pin. Thus the SYNC may clock out
the MSB of data. Subsequent bits will be clocked out by the
serial clock, SCLK. The conditions for the SYNC clocking out
the MSB of data is as follows:
With the POLARITY pin high the falling edge of
SYNC will clock
out the MSB if the serial clock is low when the
SYNC goes low.
With the POLARITY pin low the falling edge of
SYNC will clock
out the MSB if the serial clock is high when the
SYNC goes low.
Table IX. SCLK Active Edge for Different Interface Modes
Interface POLARITY DOUT DIN
Mode Pin Edge Edge
1, 2, 3 0 SCLK↑ SCLK↓
1 SCLK↓ SCLK↑
4, 5 0 SCLK↓ SCLK↑
1 SCLK↑ SCLK↓
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test regis-
ter for instance, or writing the incorrect data and corrupting the
serial interface. The SYNC pin acts as a reset. Bringing the
SYNC pin high resets the internal shift register. The first data
bit after the next SYNC falling edge will now be the first bit of a
new 16-bit transfer. It is also possible that the test register con-
tents were altered when the interface was lost. Therefore, once
the serial interface is reset, it may be necessary to write the 16-
bit word 0100 0000 0000 0010 to restore the test register to its
default value. Now the part and serial interface are completely
reset. It is always useful to retain the ability to program the
SYNC line from a port of the µController/DSP to have the
ability to reset the serial interface.
Table X summarizes the interface modes provided by the
AD7853/AD7853L. It also outlines the various µP/µC to which
the particular interface is suited.
The interface mode is determined by the serial mode selection
pins SM1 and SM2. Interface Mode 2 is the default mode. Note
that Interface Mode 1 and 2 have the same combination of SM1
and SM2. Interface Mode 1 may only be set by programming
the control register (see section on control register). External
SCLK and SYNC signals (SYNC may be hardwired low) are
required for Interfaces Modes 1, 2, and 3. In Interface Modes 4
and 5, the AD7853/AD7853L generates the SCLK and SYNC.
Some of the more popular µProcessors, µControllers, and the
DSP machines that the AD7853/AD7853L will interface to
directly are mentioned here. This does not cover all µCs, µPs
and DSPs. The interface mode of the AD7853/AD7853L that is
mentioned here for a specific µC, µP, or DSP is only a guide
and in most cases another interface mode may work just as well.
A more detailed timing description on each of the interface
modes follows.
Table X. Interface Mode Description
SM1 SM2 ␮Processor/ Interface
Pin Pin ␮Controller Mode
0 0 8XC51 1 (2-Wire)
8XL51 (DIN is an Input/
PIC17C42 Output pin)
0 0 68HC11 2 (3-Wire, SPI/QSPI)
68L11 (Default Mode)
0 1 68HC16 3 (QSPI)
PIC16C64 (External Serial
ADSP-21xx Clock, SCLK, and
DSP56000 External Frame Sync,
DSP56001 SYNC, are required)
DSP56002
DSP56L002
TMS320C30
1 0 68HC16 4 (DSP is Slave)
(AD7853/AD7853L
generates a
noncontinuous
[16 clocks] Serial
Clock, SCLK, and the
Frame Sync, SYNC)
1 1 ADSP-21xx 5 (DSP is Slave)
DSP56000 (AD7853/AD7853L
DSP56001 generates a
DSP56002 continuous Serial
DSP56L002 Clock, SCLK, and the
TMS320C20 Frame Sync, SYNC)
TMS320C25
TMS320C30
TMS320C5x
TMS320LC5x
REV. B
–24–
AD7853/AD7853L
DETAILED TIMING SECTION
Mode 1 (2-Wire 8051 Interface)
The read and writing takes place on the DIN line and the con-
version is initiated by pulsing the CONVST pin (note that in
every write cycle the 2/3 Mode bit must be set to 1). The con-
version may be started by setting the CONVST bit in the con-
trol register to 1 instead of using the CONVST line.
Below in Figure 33 and in Figure 34 are the timing diagrams for
Interface Mode 1 in Table X where we are in the 2-wire inter-
face mode. Here the DIN pin is used for both input and output
as shown. The SYNC input is level triggered active low and can
be pulsed (Figure 33) or can be constantly low (Figure 34).
In Figure 33 the part samples the input data on the rising edge
of SCLK. After the 16th rising edge of SCLK the DIN is con-
figured as an output. When the SYNC is taken high the DIN is
three-stated. Taking SYNC low disables the three-state on the
DIN pin and the first SCLK falling edge clocks out the first data
bit. Once the 16 clocks have been provided the DIN pin will
automatically revert back to an input after a time t
14
. Note that a
continuous SCLK shown by the dotted waveform in Figure 33
can be used provided that the SYNC is low for only 16 clock
pulses in each of the read and write cycles. The POLARITY pin
may be used to change the SCLK edge which the data is sampled
on and clocked out on.
In Figure 34 the SYNC line is tied low permanently and this
results in a different timing arrangement. With SYNC tied low
permanently the DIN pin will never be three-stated. The 16th
rising edge of SCLK configures the DIN pin as an input or an
output as shown in the diagram. Here no more than 16 SCLK
pulses must occur for each of the read and write operations.
If reading from and writing to the calibration registers in this
interface mode, all the selected calibration registers must be
read from or written to. The read and write operations cannot
be aborted. When reading from the calibration registers, the
DIN pin will remain as an output for the full duration of all the
calibration register read operations. When writing to the calibra-
tion registers, the DIN pin will remain as an input for the full
duration of all the calibration register write operations.
SCLK (I/P)
SYNC (I/P)
t
3
t
8
DIN (I/O)
DB15 DB0
DB0
t
3
t
11
t
6
POLARITY PIN
LOGIC HIGH
116 161
t
5A
t
12
DIN BECOMES AN INPUT
DB15
THREE-STATE
DATA READ
DATA WRITE
t
7
t
6
t
14
t
11
DIN BECOMES AN OUTPUT
t
3
= –0.4 t
SCLK
MIN (NONCONTINUOUS SCLK) –/+0.4 t
SCLK
MIN/MAX (CONTINUOUS SCLK),
t
6
= 75/115 MAX (5V/3V), t
7
= 40/60ns
MIN (5V/3V), t
8
= 20/30
MIN (5V/3V)
Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (i.e., Interface Mode 1, SM1 = SM2 = 0)
SCLK (I/P)
t
8
DIN (I/O)
DB15 DB0
DB0
t
6
116 161
DIN BECOMES AN INPUT
DB15
DATA READ
DATA WRITE
t
7
t
6
t
14
t
6
= 75/115 MAX (5V/3V), t
7
= 40/60ns
MIN (5V/3V), t
8
= 20/30
MIN (5V/3V),
t
13
= 90/130 MAX (5V/3V), t
14
= 50/90ns
MAX (5V/3V)
6
t
13
POLARITY PIN
LOGIC HIGH
Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and
SYNC
Input Tied Low
(i.e., Interface Mode 1, SM1 = SM2 = 0)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

AD7853ARZ-REEL

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Buy AD7853ARZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 12B
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