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ADV7173KSTZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADV7172/ADV7173
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Digital PAL/NTSC Video Encoder
with Six DACs (10 Bits), Color Control
and Enhanced Power Management
FEATURES
ITU-R
1
BT601/656 YCrCb to PAL/NTSC Video Encoder
Six High Quality 10-Bit Video DACs
SSAF™ (Super Sub-Alias Filter)
Advanced Power Management Features
PC’98-Compliant (TV Detect with Polling and Auto
Shutdown to Save On Power Consumption)
Low Power DAC Mode
Individual DAC ON/OFF Control
Variable DAC Output Current (5 mA–36 mA)
Ultralow Sleep Mode Current
Hue, Brightness, Contrast and Saturation Controls
CGMS (Copy Generation Management System)
WSS (Wide Screen Signalling)
NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60
YUV Betacam, MII and SMPTE/EBU N10 Output Levels
Single 27 MHz Clock Required (2 Oversampling)
80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV
EuroSCART RGB
Component YUV + CHROMA + LUMA + CVBS
EuroSCART Output RGB + CHROMA + LUMA + CVBS
Programmable Clamping Output Signal
Advanced Programmable Power-On Reset Sequencing
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
SMPTE 170M NTSC-Compatible Composite Video
ITU-R BT.470 PAL-Compatible Composite Video
Luma Sharpness Control
Programmable Luma Filters (Low-Pass [PAL/NTSC],
Notch [PAL/NTSC], Extended [SSAF], CIF and QCIF)
Programmable Chroma Filters (Low-Pass [0.65 MHz,
1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
CCIR and Square Pixel Operation
Integrated Subcarrier Locking to External Video Source
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision Antitaping Rev 7.1 (ADV7172 Only)
2
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I
2
C
®
-Compatible and Fast I
2
C)
Single Supply 5 V or 3.3 V Operation
Small 48-Lead LQFP Package
APPLICATIONS
High Performance DVD Playback Systems, Portable
Video Equipment including Digital Still Cameras and
Laptop PCs, Video Games, PC Video/Multimedia and
Digital Satellite/Cable Systems (Set-Top Boxes/IRD)
NOTES
1
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
2
The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest
Macrovision version available.
SSAF is a trademark of Analog Devices, Inc.
I
2
C is a registered trademark of Philips Corporation.
GENERAL DESCRIPTION
The ADV7172/ADV7173 is an integrated Digital Video
Encoder that converts digital CCIR-601 4:2:2 8-bit component
video data into a standard analog baseband television signal
compatible with worldwide standards.
There are six DACs available on the ADV7172/ADV7173. In
addition to the Composite output signal there is the facility to
output S-VHS Y/C Video, RGB Video and YUV Video.
The on-board SSAF (Super Sub-Alias Filter), with extended
luminance frequency response and sharp stopband attenuation,
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness control
feature allows extra luminance boost on the frequency response.
An advanced power management circuit enables optimal control
of power consumption in both normal operating modes and
power down or sleep modes. A PC’98-Compliant autodetect
feature has been added to allow the user to determine whether
or not the DACs are correctly terminated. If not, the ADV7172/
ADV7173 flags that they are not connected through the Status
bit and provides the option of automatically powering them
down, thereby reducing power consumption.
The ADV7172/ADV7173 also supports both PAL and NTSC
square pixel operation. The parts also incorporate WSS and
CGMS-A data control generation.
REV. B
ADV7172/ADV7173
–2–
FUNCTIONAL BLOCK DIAGRAM
8
8
10-BIT
DAC
R
SET1
COMP1
ADV7172/ADV7173
COLOR
DATA
P0
V
REF
R
SET2
COMP2
P7
DAC E
DAC F
DAC D
DAC A
DAC B
DAC C
BRIGHTNESS AND
CONTRAST CONTROL
+
ADD SYNC
+
INTERPOLATOR
10
LUMA
PROGRAMMABLE
FILTER
+
SHARPNESS
FILTER
SATURATION CONTROL
+
ADD BURST
+
INTERPOLATOR
10
PROGRAMMABLE
CHROMA
FILTER
10
8
8
8
REAL-TIME
CONTROL CIRCUIT
SCRESET/RTC
MODULATOR
+
HUE
CONTROL
10
10
10
10
10-BIT
DAC
10
10-BIT
DAC
10
M
U
L
T
I
P
L
E
X
E
R
Y
U
V
8
4:2:2 TO
4:4:4
INTER-
POLATOR
10 10
SIN/COS
DDS BLOCK
DAC
CONTROL
BLOCK
DAC
CONTROL
BLOCK
10-BIT
DAC
10
10
10
10
10-BIT
DAC
10
10-BIT
DAC
10
M
U
L
T
I
P
L
E
X
E
R
YUV TO
RBG
MATRIX
+
YUV
LEVEL
CONTROL
BLOCK
I
2
C MPU PORT
HSYNC
FIELD/
VSYNC
BLANK
TTX
TTXREQ
V
AA
RESET
TELETEXT
INSERTION BLOCK
YCrCb
TO
YUV
MATRIX
CLOCK CSO_HSO VSO
CLAMP
SCLOCK SDATA
ALSB
VIDEO TIMING
GENERATOR
GND
PAL
NTSC
The ADV7172/ADV7173 is designed with four color controls
(hue, contrast, brightness and saturation). All YUV formats
(SMPTE/EBU N10, MII and Betacam) are supported in both
PAL and NTSC.
The output video frames are synchronized with the incoming data
Timing Reference Codes. Optionally the encoder accepts (and can
generate) HSYNC, VSYNC, and FIELD timing signals. These
timing signals can be adjusted to change pulsewidth and position
while the part is in the master mode. The Encoder requires a
single two times pixel rate (27 MHz) clock for standard opera-
tion. Alternatively the Encoder requires a 24.5454 MHz clock
for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.
HSO/CSO and VSO TTL outputs, synchronous to the analog
output video, are also available. A programmable CLAMP out-
put signal is also available to enable clamping in either the front
or back porch of the video signal.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
The ADV7172/ADV7173 modes are set up over a 2-wire serial
bidirectional port (I
2
C-Compatible) with two slave addresses.
Functionally the ADV7173 and ADV7172 are the same with the
exception that the ADV7172 can output the Macrovision anti-
copy algorithm.
The ADV7172/ADV7173 is packaged in a 48-lead LQFP pack-
age (1.4 mm thickness).
DATA PATH DESCRIPTION
For PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb
4:2:2 Data is input via the CCIR-656-Compatible Pixel Port at a
27 MHz Data Rate. The Pixel Data is demultiplexed to form
three data paths. Y typically has a range of 16 to 235, Cr, and
Cb typically have a range of 128 ± 112; however, it is possible to
input data from 1 to 254 on both Y, Cb, and Cr. The ADV7172/
ADV7173 supports PAL (B, D, G, H, I, N, M) and NTSC
(with and without pedestal) standards. The Y data is then
manipulated by being scaled for contrast control and a setup
level is added for brightness control. The Cr, Cb data is also
scaled and saturation control is added. The appropriate Sync,
Blank and Burst levels are then added to the YCrCb data. Mac-
rovision AntiTaping (ADV7172 only), Closed-Captioning and
Teletext levels are also added to Y, and the resultant data is
interpolated to a rate of 27 MHz. The interpolated data is fil-
tered and scaled by three digital FIR Filters.
The U and V Signals are modulated by the appropriate sub-
carrier sine/cosine phases and a phase offset may be added onto
the color subcarrier during active video to allow hue adjustment.
The resulting U and V signals are then added together to make
up the chrominance signal. The luma (Y) signal can be delayed
1–3 luma cycles (each cycle is 74 ns) with respect to the chroma
signal. The luma and chroma signals are then added together to
make up the composite video signal. All edges are slew rate limited.
The YCrCb data is also used to generate RGB data with appro-
priate Sync and Blank levels.
There are six DACs on the ADV7172/ADV7173. Three of these
DACs are capable of providing 34.66 mA of current. The other
three DACs provide 8.66 mA each.
The six l0-bit DACs can be used to output:
1. Composite Video + RGB Video + LUMA + CHROMA.
2. Composite Video + YUV Video + LUMA + CHROMA.
Alternatively, each DAC can be individually powered off if not
required. A complete description of DAC output configurations
is given in Appendix 8.
Video output levels are illustrated in Appendix 6.
REV. B
–3–
ADV7172/ADV7173
(V
AA
= 5 V 5%
1
, V
REF
= 1.235 V, R
SET1,2
= 600 unless otherwise noted. All specifications T
MIN
to T
MAX
2
unless otherwise noted.)
Parameter Test Conditions
1
Min Typ Max Unit
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity
3
± 1.0 LSB
Differential Nonlinearity
3
Guaranteed Monotonic ± 1.0 LSB
DIGITAL INPUTS
Input High Voltage, V
INH
2V
Input Low Voltage, V
INL
0.8 V
Input Current, I
IN
V
IN
= 0.4 V or 2.4 V ± 1 µA
Input Capacitance, C
IN
10 pF
DIGITAL OUTPUTS
Output High Voltage, V
OH
I
SOURCE
= 400 µA 2.4 V
Output Low Voltage, V
OL
I
SINK
= 3.2 mA 0.4 V
Three-State Leakage Current 10 µA
Three-State Output Capacitance 10 pF
ANALOG OUTPUTS
Output Current (DACs A, B, C)
4
R
SET1
= 150 Ω, R
L
= 37.5 Ω 33 34.7 37 mA
Output Current (DACs A, B, C)
5
R
SET1
= 1041 Ω, R
L
= 262.5 Ω 5mA
Output Current (DACs D, E, F)
6
R
SET2
= 600 Ω, R
L
= 150 Ω 8.25 8.66 9.25 mA
Output Current (DACs D, E, F)
5
R
SET2
= 1041 Ω, R
L
= 262.5 Ω 5mA
DAC-to-DAC Matching (DACs A, B, C)
7
1 4.0 %
DAC-to-DAC Matching (DACs D, E, F)
7
1 4.0 %
Output Compliance, V
OC
0 1.4 V
Output Impedance, R
OUT
30 kΩ
Output Capacitance, C
OUT
I
OUT
= 0 mA 30 pF
VOLTAGE REFERENCE
Reference Range, V
REF
I
VREFOUT
= 20 µA 1.112 1.235 1.359 V
POWER REQUIREMENTS
V
AA
4.75 5.0 5.25 V
Normal Power Mode
I
DAC
(max)
8, 9
R
SET1,2
= 600 Ω 59 65 mA
I
DAC
(min)
8, 9
R
SET1,2
= 1041 Ω 30 mA
I
CCT
10
78 90 mA
Low Power Mode
I
DAC
(max)
11
R
SET1
= 150 Ω 64 mA
I
DAC
(min)
11
15 mA
I
CCT
10
78 90 mA
Sleep Mode
I
DAC
12
0.1 µA
I
CCT
13
0.1 µA
Power Supply Rejection Ratio COMP = 0.1 µF 0.01 0.5 %/%
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2
Temperature range T
MIN
to T
MAX
: 0°C to 70°C.
3
Characterized by design.
4
Full
drive into 75 Ω doubly terminated load.
5
Minimum drive current (used with buffered/scaled output load).
6
Full drive into 150 Ω load.
7
Specification guaranteed by characterization.
8
I
DAC
is the total current (“min” corresponds to 5 mA output per DAC, “max” corresponds to 8.66 mA output per DAC ) to drive DACs A, B, C, D, E, F. Turning off
individual DACs reduces I
DAC
correspondingly, also DACs A, B, C can be configured to output a max current of 37 mA but DAC D, E, F must be turned off.
9
All six DACs on (DAC A, B, C, D, E, F).
10
I
CCT
(Circuit Current) is the continuous current required to drive the device.
11
Only large DACs (DACs A, B, C) on per low power mode.
12
Total DAC current in Sleep Mode.
13
Total continuous current during Sleep Mode.
Specifications subject to change without notice.
5 V SPECIFICATIONS
SPECIFICATIONS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

ADV7173KSTZ-REEL

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Manufacturer:
Analog Devices Inc.
Description:
Video ICs PAL/NTSC Encoder w/ 6 DAC 10B
Lifecycle:
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