REV. B
ADV7172/ADV7173
–28–
MODE REGISTER 2 MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Mode Register 2 is an 8-bit-wide register.
Figure 46 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
RGB/YUV Control (MR20)
This bit enables the output from the DACs to be set to YUV or
RGB output video standard.
Large DACs Control (MR21)
This bit controls the output from DACs A, B, and C. When this
bit is set to “1,” composite, luma, and chroma signals are output
from DACs A, B, and C (respectively). When this bit is set to
“0,” RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)
This bit is used to switch the DAC outputs from SCART to a
EuroSCART configuration. A complete table of all DAC output
configurations is shown in Table II.
Pedestal Control (MR23)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid in the PAL mode.
Square Pixel Control (MR24)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
Standard I
2
C Control (MR25)
This bit controls the video standard used by the ADV7172/
ADV7173. When this bit is set to “1,” the video standard bits
programmed in Mode Register 0, Bits 0–1, indicate the video
standard. When this bit is set to “0,” the ADV7172/ADV7173
is forced into the standard selected by the NTSC_PAL pin.
Pixel Data Valid Control (MR26)
After reset, this bit has the value “0” and the pixel data input to
the encoder is blanked such that a black screen is output from
the DACs. The ADV7172/ADV7173 will be set to master mode
timing. When this bit is set to “1” by the user (via the I
2
C),
pixel data passes to the pins and the encoder reverts to the
timing mode defined by Timing Mode Register 0.
Sleep Mode Control (MR27)
When this bit is set (“1”), sleep mode is enabled. With this
mode enabled the ADV7172/ADV7173 power consumption is
reduced to less than 20 µA. The I
2
C registers can be written to
and read from when the ADV7172/ADV7173 is in sleep mode.
If “0” is written to MR27 when the device is in sleep mode, the
ADV7172/ADV7173 will come out of sleep mode and resume
normal operation. Also, if the reset signal is applied during sleep
mode, the ADV7172/ADV7173 will come out of sleep mode
and resume normal operation. This mode will only operate
when MR60 is set to a Logic “1”; otherwise sleep mode is con-
trolled by the PAL_NTSC and SCRESET/RTC pin.
MR21
MR27 MR22MR23MR26 MR25 MR24 MR20
SLEEP MODE
CONTROL
0 DISABLE
1 ENABLE
MR27
STANDARD I
2
C
CONTROL
0 DISABLE
1 ENABLE
MR25
PIXEL DATA VALID
CONTROL
0 DISABLE
1 ENABLE
MR26
SQUARE PIXEL
CONTROL
0 DISABLE
1 ENABLE
MR24
SCART ENABLE
CONTROL
0 DISABLE
1 ENABLE
MR22
RGB/YUV
CONTROL
0 RGB OUTPUT
1 YUV OUTPUT
MR20
PEDESTAL
CONTROL
0 PEDESTAL ON
1 PEDESTAL OFF
MR23
LARGE DACs
CONTROL
0 RGB/YUV/COMP
1 COMP/LUMA/CHROMA
MR21
Figure 46. Mode Register 2 (MR2)
Table II. DAC Output Configuration Matrix
MR22 MR21 MR20 DAC A DAC B DAC C DAC D DAC E DAC F
0 0 0 G B R CVBS LUMA CHROMA
0 0 1 Y U V CVBS LUMA CHROMA
0 1 0 CVBS LUMA CHROMA G B R
0 1 1 CVBS LUMA CHROMA Y U V
1 0 0 CVBS B R G LUMA CHROMA
1 0 1 CVBS U V Y LUMA CHROMA
1 1 0 CVBS LUMA CHROMA G B R
1 1 1 CVBS LUMA CHROMA Y U V
