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ADV7173KSTZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
REV. B
ADV7172/ADV7173
–31–
MODE REGISTER 5 MR5 (MR57–MR50)
(Address (SR4-SR0) = 05H)
Mode Register 5 is an 8-bit-wide register. Figure 49 shows the
various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)
This bit controls the Y output level on the ADV7172/ADV7173.
If this bit is set (“0”), the encoder outputs SMPTE levels when
configured in PAL mode and Betacam levels when configured
in NTSC mode. If this bit is set (“1”), the encoder outputs
Betacam levels when configured in PAL mode and SMPTE
levels when configured in NTSC mode.
UV-Levels Control (MR52–MR51)
These bits control the U and V output levels on the ADV7172/
ADV7173. It is possible to have UV levels with a peak-peak
amplitude of either 700 mV (MR52 + MR51 = “01”) or 1000 mV
(MR52 + MR51 = “10”) in NTSC and PAL. It is also possible
to have default values of 934 mV for NTSC and 700 mV for
PAL (MR52 + MR51 = “00”).
RGB Sync (MR53)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay (MR55–MR54)
These bits control the delay or advance of the CLAMP signal in
the front or back porch of the ADV7172/ADV7173. It is possible
to delay or advance the pulse by 0, 1, 2 or 3 clock cycles.
Clamp Delay Direction (MR56)
This bit controls a positive or negative delay in the CLAMP
signal. If this bit is set (“1”), the delay is negative. If it is not set
(“0”), the delay is positive.
Clamp Position (MR57)
This bit controls the position of the CLAMP signal. If this bit is
set (“1”), the CLAMP signal is located in the back porch posi-
tion. If this bit is set to (“0”), the CLAMP signal is located in
the front porch position.
MR51
MR50
MR57
MR52MR54 MR53MR55MR56
CLAMP DELAY
DIRECTION
0 POSITIVE
1 NEGATIVE
MR56
CLAMP POSITION
0 FRONT PORCH
1 BACK PORCH
MR57
CLAMP DELAY
0 0 NO DELAY
011 PCLK
102 PCLK
113 PCLK
MR55 MR54
UV-LEVELS CONTROL
0 0 DEFAULT LEVELS
0 1 700mV
1 0 1000mV
1 1 RESERVED
MR52 MR51
RGB
SYNC
0 DISABLE
1 ENABLE
MR53
Y-LEVEL
CONTROL
0 DISABLE
1 ENABLE
MR50
Figure 49. Mode Register 5 (MR5)
REV. B
ADV7172/ADV7173
–32–
MODE REGISTER 6 MR6 (MR67–MR60)
(Address (SR4–SR0) = 06H)
Mode Register 6 is an 8-bit-wide register. Figure 50 shows the
various operations under the control of Mode Register 6.
MR6 BIT DESCRIPTION
Power-Up Sleep Mode Control (MR60)
After reset this bit is set to “0,” if both SCRESET/RTC and
NTSC_PAL pins are tied high, the part will power-up in sleep
mode (to facilitate low power consumption before the I
2
C is
initialized). When this bit is set to “1” (via the I
2
C), sleep mode
control passes to Mode Register 2, Bit 7.
Reserved (MR61)
A Logic “0” must be written to this bit.
Luma Autodetect Control (MR62)
This bit controls which mode of autodetect operation is being
used on the luma DAC (DAC B) on the ADV7172/ADV7173.
If this bit is set (“0”), Mode 0 is on; if this bit is set (“1”), then
Mode 1 is being used.
Composite Autodetect Control (MR63)
This bit controls which mode of autodetect operation is being
used on the composite DAC (DAC A) on the ADV7172/
ADV7173. If this bit is set (“0”), Mode 0 is on; if this bit is set
(“1”), then Mode 1 is being used.
DAC Termination Control (MR64)
This bit controls the load termination resistance detected by the
autodetect functionality. If this bit is set (“0”), the autodetect
feature is used to determine if a 75 Ω termination is present. If
this bit is set to (“1”), the autodetect feature is used to indicate
if a 150 Ω termination is present.
Reserved (MR65)
A Logic “0” must be written to this bit.
Luma DAC Status Bit (MR66)
This bit is a read-only status bit for the autodetect feature of
the ADV7172/ADV7173 and may be read to check whether
or not the composite DAC is terminated. If this bit is set (“1”),
there is no termination; if this bit is set (“0”), the composite DAC
is terminated.
Composite DAC Status Bit (MR67)
This bit is a read only status bit for the autodetect feature of the
ADV7172/ADV7173 and may be read to check whether or not
the luma DAC is terminated. If this bit is set (“1”), there is no
termination. If this bit is set (“0”), the luma DAC is terminated.
MR61
MR60
MR67
MR62MR64 MR63MR65MR66
COMPOSITE
DAC STATUS BIT
0 NOT TERMINATED
1 TERMINATED
MR67
DAC TERMINATION
CONTROL
01 MODE
12 MODE
MR64
LUMA DAC
STATUS BIT
0 NOT TERMINATED
1 TERMINATED
MR66
COMP AUTODETECT
CONTROL
0 MODE 0
1 MODE 1
MR63
LUMA AUTODETECT
CONTROL
0 MODE 0
1 MODE 1
MR62
MR61
ZERO SHOULD
BE WRITTEN TO
THIS BIT
POWER-UP SLEEP
MODE CONTROL
0 ENABLE
1 DISABLE
MR60
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR65
Figure 50. Mode Register 6 (MR6)
REV. B
ADV7172/ADV7173
–33–
MODE REGISTER 7 MR7 (MR77–MR70)
(Address (SR4–SR0) = 07H)
Mode Register 7 is an 8-bit-wide register. Figure 51 shows the
various operations under the control of Mode Register 7.
MR7 BIT DESCRIPTION
Color Control Enable (MR70)
This bit is used to enable control of contrast and saturation of
color. If this bit is set (“1”), color controls are enabled; if this
bit is set (“0”), the color control features are disabled.
Luma Saturation Control (MR71)
When this bit is set (“1”), the luma signal will be clipped if it
reaches a limit that corresponds to an input luma value of
255 after scaling by the contrast control. This prevents the
chrominance component of the composite video signal being
clipped if the amplitude of the luma is too high. When this bit is
set (“0”), this control is disabled.
Hue Adjust Enable (MR72)
This bit is used to enable hue adjustment on the composite and
chroma output signals of the ADV7172/ADV7173. When this
bit is set (“1”), the hue of the color is adjusted by the phase
offset described in the Hue Control Register. When this bit is
set (“0”) hue adjustment is disabled.
Brightness Enable Control (MR73)
This bit is used to enable brightness control on the ADV7172/
ADV7173 by enabling the programmable “setup level” or ped-
estal described in the Brightness Control Register to be added to
the scaled Y data. When this bit is set (“1”), brightness control
is enabled. When this bit is set (“0”), brightness control is disabled.
Sharpness Response Enable (MR74)
This bit is used to enable the sharpness of the luminance signal
on the ADV7172/ADV7173 (MR04–MR02 = 100). The various
responses of the filter are determined by the Sharpness Response
Register. When this bit is set (“1”) the luma response is altered
by the amount described in the Sharpness Response Register.
When this bit is set (“0”), the sharpness control is disabled (see
Figures 19, 20, and 21 for luma signal responses).
CSO_HSO Output Control (MR75)
This bit is used to determine whether HSO or CSO TTL out-
put signal is output at the CSO_HSO pin. If this bit is set (“1”),
then the CSO TTL signal is output. If this bit is set (“0”), then
the HSO TTL signal is output.
Reserved (MR77–MR76)
A Logic “0” must be written to these bits.
MR71 MR70MR77 MR72MR74 MR73MR75MR76
MR77 MR76
ZERO SHOULD
BE WRITTEN TO
THESE BITS
CSO_HSO
OUTPUT CONTROL
0 HSO OUT
1 CSO OUT
MR75
BRIGHTNESS
ENABLE CONTROL
0 DISABLE
1 ENABLE
MR73
LUMA SATURATION
CONTROL
0 DISABLE
1 ENABLE
MR71
SHARPNESS
RESPONSE ENABLE
0 DISABLE
1 ENABLE
MR74
HUE ADJUST
ENABLE
0 DISABLE
1 ENABLE
MR72
COLOR CONTROL
ENABLE
0 DISABLE
1 ENABLE
MR70
Figure 51. Mode Register 7 (MR7)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

ADV7173KSTZ-REEL

Mfr. #:
Buy ADV7173KSTZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Video ICs PAL/NTSC Encoder w/ 6 DAC 10B
Lifecycle:
New from this manufacturer.
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