REV. B
ADV7172/ADV7173
–40–
BRIGHTNESS CONTROL REGISTERS (BCR)
(Address (SR5–SR0) = 21H)
The brightness control register is an 8-bit-wide register which
allows brightness control. Figure 66 shows the operation under
control of this register.
BCR BIT DESCRIPTION
Reserved (BCR7–BCR5)
A Logic “0” must be written to these bits.
Brightness Value (BCR4–BCR0)
These five bits represent the value required to vary the “brightness
level” or pedestal added to the luma data. The available range is
from 0 IRE to 7.5 IRE in 18 steps. A value of 18 (10010) corre-
sponds to 7.5 IRE setup level added onto the pixel data. This
brightness control is possible in both PAL and NTSC.
SHARPNESS RESPONSE REGISTER (PR)
(Address (SR5-SR0) = 22H)
The sharpness response register is an 8-bit-wide register. The
four MSBs are set to “0.” The four LSBs are written to in order
to select a desired filter response. Figure 67 shows the operation
under control of this register.
PR BIT DESCRIPTION
Reserved (PR7–PR4)
A Logic “0” must be written to these bits.
Sharpness Response Value (PR3–PR0)
These four bits are used to select the desired luma filter response.
The option of twelve responses is given supporting a gain boost/
attenuation in the range –4 dB to +4 dB. The value 12 (1100)
written to these four bits corresponds to a boost of +4 dB while
the value 0 (0000) corresponds to –4 dB. For normal opera-
tion these four bits are set to 6 (0110). Refer to Figures 19–21
for filter plots.
BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0
BCR4BCR0
BRIGHTNESS VALUE
BCR7BCR5
ZERO SHOULD
BE WRITTEN
TO THESE BITS
Figure 66. Brightness Control Register
PR7 PR6 PR5 PR4
PR3 PR2 PR1 PR0
PR3PR0
SHARPNESS RESPONSE
VALUE
PR7PR4
ZERO SHOULD
BE WRITTEN
TO THESE BITS
Figure 67. Sharpness Response Register
REV. B
ADV7172/ADV7173
–41–
The ADV7172/ADV7173 is a highly integrated circuit containing
both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be applied
to the system level design so that high speed, accurate performance
is achieved. The Recommended Analog Circuit Layout shows
the analog interface between the device and monitor.
The layout should be optimized for lowest noise on the ADV7172/
ADV7173 power and ground lines by shielding the digital inputs
and providing good decoupling. The lead length between groups
of V
AA
and GND pins should by minimized to minimize induc-
tive ringing.
Ground Planes
The ground plane should encompass all ADV7172/ADV7173
ground pins, voltage reference circuitry, power supply bypass cir-
cuitry for the ADV7172/ADV7173, the analog output traces, and
all the digital signal traces leading up to the ADV7172/ADV7173.
The ground plane is the board’s common ground plane.
Power Planes
The ADV7172/ADV7173, and any associated analog circuitry,
should have its own power plane, referred to as the analog
power plane (V
AA
). This power plane should be connected to
the regular PCB power plane (V
CC
) at a single point through a
ferrite bead. This bead should be located within three inches of
the ADV7172/ADV7173.
The metallization gap separating device power plane and
board power plane should be as narrow as possible to mini-
mize the obstruction to the flow of heat from the device into
the general board.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7172/ADV7173 power pins and voltage
reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common-mode.
Supply Decoupling
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
obtained with 0.1 µF ceramic capacitor decoupling. Each group
of V
AA
pins on the ADV7172/ADV7173 must have at least one
0.1 µF decoupling capacitor to GND. These capacitors should
be placed as close to the device as possible.
It is important to note that while the ADV7172/ADV7173
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduc-
ing power supply noise and consider using a three-terminal voltage
regulator for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs to the ADV7172/ADV7173 should be iso-
lated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay the
analog power plane.
Due to the high clock rates involved, long clock lines to the
ADV7172/ADV7173 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (V
CC
) and not the
analog power plane.
Analog Signal Interconnect
The ADV7172/ADV7173 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75 load
resistor connected to GND. These resistors should be placed
as close as possible to the ADV7172/ADV7173 to minimize
reflections.
The ADV7172/ADV7173 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
REV. B
ADV7172/ADV7173
–42–
0.1F
5V (V
AA
)
23
COMP2
35
33
4k
5V (V
CC
)
150
21
4k
5V (V
CC
)
MPU BUS
48
44
14
16
15
12, 13, 18, 26, 31, 47
17
20
38
1, 11, 19, 27, 30, 32, 34, 46
0.1F 0.01F
5V (V
AA
)
10k
5V (V
AA
)
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
37
GND
ALSB
HSYNC
FIELD/VSYNC
BLANK
RESET
CLOCK
R
SET1
SDATA
SCLOCK
DAC A
V
AA
V
REF
P0
P7
75
75
39
SCRESET/RTC
ADV7172/
ADV7173
UNUSED
INPUTS
SHOULD BE
GROUNDED
DAC B
100
100
5V (V
AA
)
RESET
41
TTX
TTXREQ
10k
5V (V
AA
)
TTX
TTXREQ
0.1F
36
COMP1
43
42
VSO
CLAMP
PAL_NTSC
29
28
DAC C
75
300
DAC D
25
24
DAC E
300
DAC F
600
22R
SET2
9
2
10
300
45
40
27MHz CLOCK
(SAME CLOCK AS
USED BY MPEG2
DECODER)
CSO_HSO
4k
4.7F
Figure 68. Recommended Analog Circuit Layout

ADV7173KSTZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs PAL/NTSC Encoder w/ 6 DAC 10B
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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