REV. B
ADV7172/ADV7173
–25–
The ADV7172/ADV7173 acts as a standard slave device on the
bus. The data on the SDATA pin is eight bits long, supporting
the 7-bit addresses plus the R/W bit. It interprets the first byte
as the device address and the second byte as the starting sub-
address. The subaddresses auto increment allows data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
Stop and Start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then these cause an
immediate jump to the idle condition. During a given SCLOCK
high period, the user should issue only one start condition, one
stop condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7172/ADV7173 will not issue an acknowledge and will
return to the idle condition. If, in autoincrement mode, the user
exceeds the highest subaddress, the following action will be taken:
1. In Read Mode the highest subaddress register contents
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDATA line is not
pulled low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will not be loaded
into any subaddress register, a no-acknowledge will be issued
by the ADV7172/ADV7173 and the part will return to the
idle condition.
Figure 41 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
1-7 8 9 1-7 8 9 1-7 8 9 PS
START ADDR
R/W
ACK
SUBADDRESS ACK DATA ACK
STOP
SDATA
SCLOCK
Figure 41. Bus Data Transfer
Figure 42 shows bus write and read sequences.
REGISTER ACCESSES
The MPU can write to or read from all of the registers of the
ADV7172/ADV7173 except the Subaddress Register, which is a
write-only register. The Subaddress Register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
Subaddress Register. A read/write operation is then performed
from/to the target address, which then increments to the next
address until a Stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcar-
rier phase register, timing registers, closed captioning extended
data registers, closed captioning data registers, NTSC pedestal
Control/PAL teletext control registers, CGMS/WSS registers,
contrast register, U- or V-scale registers, hue adjust register,
brightness control register and sharpness control register in
terms of its configuration. All registers can be read from as well
as written to.
DATA A(S)S SLAVE ADDR A(S) SUB ADDR A(S)
LSB = 0
LSB = 1
DATA
A(S)
P
S
SLAVE ADDR A(S) SUB ADDR
A(S)
S
SLAVE ADDR A(S) DATA
A(M )
DATA P
WRITE
SEQUENCE
READ
SEQUENCE
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(M)
Figure 42. Write and Read Sequences
