REV. B
ADV7172/ADV7173
–16–
H/LTRANSITION
COUNT START
LOW
128
RTC
TIME SLOT: 01
14
67 68
NOT USED IN
ADV7172/ADV7173
19
VALID
SAMPLE
INVALID
SAMPLE
FSCPLL INCREMENT
1
8/LLC
5 BITS
RESERVED
SEQUENCE
BIT
2
RESET
BIT
3
RESERVED
4 BITS
RESERVED
21
013
14 BITS
RESERVED
0
NOTES
1
F
SC
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7172/ADV7173 FSC DDS REGISTER IS F
SC
PLL INCREMENT BITS 21:0 PLUS BITS 0:9
OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE
ADV7172/ADV7173.
2
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
3
RESET BIT
RESET ADV7172/ADV7173’s DDS
COMPOSITE
VIDEO
e.g., VCR
OR CABLE
HSYNC
FIELD/VSYNC
CLOCK
GREEN/COMPOSITE/Y
RED/CHROMA/V
BLUE/LUMA/U
GREEN/COMPOSITE/Y
BLUE/LUMA/U
RED/CHROMA/V
ADV7172/ADV7173
P7–P0
SCRESET/RTC
VIDEO
DECODER
ADV7185
LCC1
GLL
P19-P12
Figure 22. RTC Timing and Connections
Mode 0 (CCIR–656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7172/ADV7173 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data.
All timing information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 23. The HSYNC, FIELD/VSYNC, and BLANK
(if not used) pins should be tied high during this mode.
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
Y
C
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
268 CLOCK
1440 CLOCK
4 CLOCK
4 CLOCK
280 CLOCK
1440 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
Figure 23. Timing Mode 0 (Slave Mode)
